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Tue, 21 Jul 2026 12:48:40 -0700 From: Nicolin Chen To: , , CC: , , , , , , , Subject: [PATCH v9 06/12] iommu/arm-smmu-v3-kexec: Add a CD table parse helper Date: Tue, 21 Jul 2026 12:48:15 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D8:EE_|SJ1PR12MB6170:EE_ X-MS-Office365-Filtering-Correlation-Id: 5777252d-afc2-4626-67c6-08dee7611eea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|23010399003|82310400026|36860700016|6133799003|22082099003|18002099003|3023799007|56012099006|11063799006|5023799004|10067099003; X-Microsoft-Antispam-Message-Info: KRaKwiVu8nJTwGfvcKQpQoyKxfbb8o/vM4Te1+yRJVBbY9tTA4XdrjHmd7gBCSY+u/wvg9bBt8B2/YYebsBUMrETRHunx6O6HbiKsHym2vxZYyfBOGI/6IXF3k++yjY6bSmHjjXUOIMB+5iWmM4hrb6AUpLtHRIfUEy/Cb/WirJOmgqr9rLajwA3Ncf1PQkJ0dUhAlt5ZfiANV+V2DP88Ce4Zcwl7wGxDPXWL3kD5yuaLmM/xnSrY/VDVj7dhzcwQqG9mqBP7bRMJb2ZkrklJtoBoCj4OIKd/hOJoIEWHd9NrmFTgkEQaHdYvW3qdDGCqOsGVxxRa6gib1YfEjHfjYtwNyTbS8MZhq8RF3kqTnUhtysrnpBeCTlpy4OYGRwLQLN8mNh4q3VY0LgIcICR1bUMfqvj5d+CbvenKrgG9RowLhsj4CaYKH7GrPuSeY7FadkdRZqenChpB/HYNHhF/UMiMMNRRY9ijeYOphkDliajuU4KhqQJSChbEciz0z7/956U6GE0nA+FyBcple5TQwHk5agAmy+bf+m+mWWsaUnUe1c1Q9mPWDJmY1qlpZqKrxEgxu7dDACrTdxS7CZIEhyeVhVHgilvnZYt2BKeYIOPvItRbhm26iII/JUH6njUjXEREMdtdjZthoTAvTwuQYKXHZACb/j4EpIP5CaelPaBpa+bD2uh1AYy6BcE1ecySw7aRQ+aDw2rNye1OuKEbQ== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(23010399003)(82310400026)(36860700016)(6133799003)(22082099003)(18002099003)(3023799007)(56012099006)(11063799006)(5023799004)(10067099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /KRny7zZIkO+5F3iKYwJzzsjGPJF40ZwkbmXX6m8rtEuVZqpMQJLF+uZ317nIO05PEtLqRbfF3n4TXTQpJd6AUtRXfuAEJ877MpuUNb66mGcsJaLrxu9qjy4XFgdnheg6/1S7z7XDOvbcbe7AIdpDtJ0ytvl02uNnYJtcyhuXenBapYzeQYHVyHv13yOb1VYdg7LAkwEpIQW2FcqVOyC75ZXLLsbHcdnhSwp36GrGqne8SPqzm9yuYFurmiBcN5SnX9kmlDx6CG19zSeeDQEa3JcUk7iSdx89iMUtMi/UOQrl7SDq8Qp2BLr8p7aQ1VRnM8oYl41q2vb9DHliLXo/Zkth2MVuAgcqB5cl5UwKxHnAPKhsyJb/rhtlV9snwo/ULNMTUfCcB6dy+f79XNFIeoOPEy9I1Xl5YcE/fJlilpe0lOh37VWimxOI4Dj7ifF X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jul 2026 19:49:04.8409 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5777252d-afc2-4626-67c6-08dee7611eea X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D8.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6170 An S1 STE points to a CD table that both of the kexec flavors decode: the kdump adoption scans the CD table to reserve all the in-use ASIDs, and the live-update restoration claims the CD table via the KHO restore API. Add another read-only helper to the arm-smmu-v3-kexec.c: - arm_smmu_kexec_check_ste_cdtab() It validates the CD table geometry in an S1 STE against this kernel's own ssid_bits and the 2-level HW capability. And it accepts a linear CD table on the 2-level capable HW too, since a previous kernel might have used one, like the linear stream table. Assisted-by: Claude:claude-fable-5 Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 ++ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c | 42 +++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 6ef307335d80c..183c617ecb273 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1249,6 +1249,9 @@ int arm_smmu_kexec_parse_strtab_linear(struct arm_smmu_device *smmu, int arm_smmu_kexec_check_strtab_l1_desc(struct arm_smmu_device *smmu, u64 l1_desc, u32 idx, phys_addr_t *l2_base); +int arm_smmu_kexec_check_ste_cdtab(struct arm_smmu_device *smmu, u64 ste0, + phys_addr_t *cdtab, u32 *s1fmt, + u32 *max_contexts); #endif /* CONFIG_ARM_SMMU_V3_KEXEC */ #ifdef CONFIG_CRASH_DUMP diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c index 5346132529427..5ad1fe1922eec 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c @@ -157,3 +157,45 @@ int arm_smmu_kexec_check_strtab_l1_desc(struct arm_smmu_device *smmu, *l2_base = base; return 0; } + +/** + * arm_smmu_kexec_check_ste_cdtab() - Decode the CD table geometry of an STE + * @smmu: SMMU device of this kernel + * @ste0: first 64 bits of the previous kernel's S1 STE + * @cdtab: pointer to return the CD table's physical address + * @s1fmt: pointer to return the CD table format + * @max_contexts: pointer to return the number of CDs + * + * Note that a linear CD table on the 2-level capable hardware is accepted, as a + * previous kernel might have used one, like the linear stream table. + * + * Also, as the CD tables are supposed to be read-only, @cdtab is not validated + * against the table size, but only carries the field's own 64-byte alignment. + * + * Return: 0 on success with the three outputs set, or -EINVAL on a bad geometry + */ +int arm_smmu_kexec_check_ste_cdtab(struct arm_smmu_device *smmu, u64 ste0, + phys_addr_t *cdtab, u32 *s1fmt, + u32 *max_contexts) +{ + phys_addr_t base = ste0 & STRTAB_STE_0_S1CTXPTR_MASK; + u32 s1cdmax = FIELD_GET(STRTAB_STE_0_S1CDMAX, ste0); + u32 fmt = FIELD_GET(STRTAB_STE_0_S1FMT, ste0); + + if (!base || s1cdmax > smmu->ssid_bits) + return -EINVAL; + + if (fmt != STRTAB_STE_0_S1FMT_LINEAR && + fmt != STRTAB_STE_0_S1FMT_64K_L2) + return -EINVAL; + + /* Both kernels run on the same HW, so a genuine STE never has this */ + if (fmt == STRTAB_STE_0_S1FMT_64K_L2 && + !(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB)) + return -EINVAL; + + *cdtab = base; + *s1fmt = fmt; + *max_contexts = 1U << s1cdmax; + return 0; +} -- 2.43.0