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Wed, 16 Aug 2023 07:06:03 GMT Received: from hu-pkondeti-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Wed, 16 Aug 2023 00:05:57 -0700 Date: Wed, 16 Aug 2023 12:35:54 +0530 From: Pavan Kondeti To: Krishna chaitanya chundru CC: , , , , , , , , , , , Andy Gross , "Bjorn Andersson" , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" Subject: Re: [PATCH v1 2/3] arm64: dts: qcom: sm8450: Add opp table support to PCIe Message-ID: References: <1692102408-7010-1-git-send-email-quic_krichai@quicinc.com> <1692102408-7010-3-git-send-email-quic_krichai@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <1692102408-7010-3-git-send-email-quic_krichai@quicinc.com> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: rDErzUi5WBgE6QMXZM7TE95s7FWEECSZ X-Proofpoint-GUID: rDErzUi5WBgE6QMXZM7TE95s7FWEECSZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-16_04,2023-08-15_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 spamscore=0 malwarescore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 mlxlogscore=878 bulkscore=0 impostorscore=0 clxscore=1015 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308160063 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Aug 15, 2023 at 05:56:47PM +0530, Krishna chaitanya chundru wrote: > PCIe needs to choose the appropriate performance state of RPMH power > domain based upon the PCIe gen speed. > > So, let's add the OPP table support to specify RPMH performance states. > > Signed-off-by: Krishna chaitanya chundru > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 47 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 47 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 595533a..681ea9c 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -381,6 +381,49 @@ > }; > }; > > + pcie0_opp_table: opp-table-pcie0 { > + compatible = "operating-points-v2"; > + > + opp-2500000 { > + opp-hz = /bits/ 64 <2500000>; > + opp-level = ; > + }; > + > + opp-5000000 { > + opp-hz = /bits/ 64 <5000000>; > + opp-level = ; > + }; > + > + opp-8000000 { > + opp-hz = /bits/ 64 <8000000>; > + opp-level = ; > + }; > + }; > + > + pcie1_opp_table: opp-table-pcie1 { > + compatible = "operating-points-v2"; > + > + opp-2500000 { > + opp-hz = /bits/ 64 <2500000>; > + opp-level = ; > + }; > + > + opp-5000000 { > + opp-hz = /bits/ 64 <5000000>; > + opp-level = ; > + }; > + > + opp-8000000 { > + opp-hz = /bits/ 64 <8000000>; > + opp-level = ; > + }; > + > + opp-16000000 { > + opp-hz = /bits/ 64 <16000000>; > + opp-level = ; > + }; > + }; > + Should not we using required-opps property to pass the rpmhpd_opp_xxx phandle so that when this OPP is selected based on your clock rate, the appropriate OPP (voltage) would be selected on the RPMH side? Please see SDHCI/MMC voting (sdhc2_opp_table) as an example. Thanks, Pavan