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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b842a56c552sm1089465666b.68.2026.01.09.02.44.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Jan 2026 02:44:51 -0800 (PST) Message-ID: Date: Fri, 9 Jan 2026 11:44:48 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] drm/msm/dpu: fix mismatch between power and frequency To: yuanjie yang , robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, krzysztof.kozlowski@linaro.org Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com References: <20260109083808.1047-1-yuanjie.yang@oss.qualcomm.com> <20260109083808.1047-2-yuanjie.yang@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260109083808.1047-2-yuanjie.yang@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA5MDA3OCBTYWx0ZWRfXya+1alL8Z0fF t7woVmjAJSQ7bqRgmXXtJuzF3KEUfpEK39vjlpQOacUQ/Q6+PugAZVdVylpK53ttJ2qaj58xg+F Y+faCE/bPUPs5WznBNEzrVA9z3PBkvmz0sU8TiyYbAguopPQq81WJuhFqOhfi2jF68XqpP2NAEJ 8HaU753cKf40WSaa4qLAWI/wFiFrJ9IheU7VQp9TZ4JaYMEgYFQcrIawCGQUL2hTtfERIHoSrua MO3QBp3bimrnCzD6eQByiAQZyx1HeLmh/5/0mcssyjsdmw62fgvnO1WPpu80mLAztgcTGWbKdv3 4yzmNadF22RQEu/WbbNaKcyUtV7DpbW8x9hry7Y686cBIXhLHo2wWqfHNNnCFR65dxZhkGBELTj X1ck2+AA3DS5czeXJQ43J+jT58CkL+jfM/9czu6d7V5rMYG0dvtjkfDmpyeiGazn8ZFOIPSTzpV hIidROT29mmszRoEU7Q== X-Proofpoint-GUID: iO8AwVuwNKGK_6-Z7enFHFZL9uNPVQM6 X-Proofpoint-ORIG-GUID: iO8AwVuwNKGK_6-Z7enFHFZL9uNPVQM6 X-Authority-Analysis: v=2.4 cv=Xtf3+FF9 c=1 sm=1 tr=0 ts=6960dc25 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=MqSUJ6ohGVtzaGjW0LAA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-09_03,2026-01-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 malwarescore=0 adultscore=0 clxscore=1015 suspectscore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601090078 On 1/9/26 9:38 AM, yuanjie yang wrote: > From: Yuanjie Yang > > During DPU runtime suspend, calling dev_pm_opp_set_rate(dev, 0) drops > the MMCX rail to MIN_SVS while the core clock frequency remains at its > original (highest) rate. When runtime resume re-enables the clock, this > may result in a mismatch between the rail voltage and the clock rate. > > For example, in the DPU bind path, the sequence could be: > cpu0: dev_sync_state -> rpmhpd_sync_state > cpu1: dpu_kms_hw_init > timeline 0 ------------------------------------------------> t > > After rpmhpd_sync_state, the voltage performance is no longer guaranteed > to stay at the highest level. During dpu_kms_hw_init, calling > dev_pm_opp_set_rate(dev, 0) drops the voltage, causing the MMCX rail to > fall to MIN_SVS while the core clock is still at its maximum frequency. > When the power is re-enabled, only the clock is enabled, leading to a > situation where the MMCX rail is at MIN_SVS but the core clock is at its > highest rate. In this state, the rail cannot sustain the clock rate, > which may cause instability or system crash. So what this message essentially says is that dev_pm_opp_set_rate(dev, 0) doesn't actually set the rate of "0" (or any other rate, unless opp-level is at play), nor does it disable the clock. Seems like a couple of our drivers make this oversight.. I see that originally calling dev_pm_opp_set_rate(dev, 0) was forbidden, up until Commit cd7ea582866f ("opp: Make dev_pm_opp_set_rate() handle freq = 0 to drop performance votes").. In fact, $ rg 'dev_pm_opp_set_rate\(.*, 0\)' returns exclusively Qualcomm drivers where I believe the intention is always to disable the clock.. perhaps we should just do that instead. We don't have to worry about setting F_MIN beforehand, because a disabled clock won't be eating up power and when enabling it back up, calling opp_set_rate with a non-zero frequency will bring back the rails to a suitable level Konrad