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Mon, 08 Sep 2025 09:49:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF1It0dv5BR9m68fGngu0EK/yeg+C603sZAq9ZhSJtilPcPbfpfhlLXJ7uaZ1TlMyG2wUj1rw== X-Received: by 2002:a05:6a20:72a2:b0:243:d1bd:fbbb with SMTP id adf61e73a8af0-2534775a1e6mr13236761637.59.1757350158859; Mon, 08 Sep 2025 09:49:18 -0700 (PDT) Received: from [10.91.118.43] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7722a4e5b44sm29578565b3a.88.2025.09.08.09.49.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Sep 2025 09:49:18 -0700 (PDT) Message-ID: Date: Mon, 8 Sep 2025 22:19:13 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 03/16] drm/msm/a6xx: Poll additional DRV status To: Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Antonino Maniscalco , Neil Armstrong References: <20250908-ifpc-support-v2-0-631b1080bf91@oss.qualcomm.com> <20250908-ifpc-support-v2-3-631b1080bf91@oss.qualcomm.com> <77cfd9d7-c3f1-4e0b-8cf4-8567611c3a9d@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: <77cfd9d7-c3f1-4e0b-8cf4-8567611c3a9d@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=FN4bx/os c=1 sm=1 tr=0 ts=68bf0910 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=MmCsC9iFmiawHEAYgzAA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: o5YN_apS84RIQZXfPSmPsx7NZ5XRQiZb X-Proofpoint-GUID: o5YN_apS84RIQZXfPSmPsx7NZ5XRQiZb X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA4MDA5NCBTYWx0ZWRfXzRfNAc+Tw4y1 NICVRkz8cDBr2sSIWk8TmPkAvjMcwDyc5tyAfGzzhBgEVFzydlRt1YJTZXdR2zHuGiBjorgct8+ 90PWm4NUnwcTeS5WzcT04XcqXXv7o3LTTUe6oZzqwBu9erMBwhQmJfWoYhPJL9uyf5YmPR1MrzC jMdbGluW2pdxZAw2rVcoZgSzgsaYlheMzN1Q0GcG0Pl2Bk+IouNHmi490/7OzRox2lXAa388xD7 Ao7Cl3Oi/yQzpyLhuO+wn7Hc4ysLrMh2+dksdCGo3N3cQrdMF7Bryh7sZWn1CElqFYLrCkJUj9o lyc8R2wkwp6KXxgWc3+RywhHgBC7ffeLiRZ9ZGBW0EClCscUIGqGd1+xRGvMN3mH6EsVQLnoPpa v/bbmdTu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 clxscore=1015 phishscore=0 adultscore=0 bulkscore=0 impostorscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509080094 On 9/8/2025 8:48 PM, Konrad Dybcio wrote: > On 9/8/25 10:26 AM, Akhil P Oommen wrote: >> A7XX_GEN2 generation has additional TCS slots. Poll the respective >> DRV status registers before pm suspend. >> >> Fixes: 1f8c29e80066 ("drm/msm/a6xx: Add A740 support") >> Signed-off-by: Akhil P Oommen >> --- >> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 16 ++++++++++++++++ >> 1 file changed, 16 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> index bb30b11175737e04d4bfd6bfa5470d6365c520fa..06870f6596a7cb045deecaff3c95fba32ee84d52 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> @@ -987,6 +987,22 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) >> val, (val & 1), 100, 10000); >> gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS + seqmem_off, >> val, (val & 1), 100, 1000); >> + >> + if (!adreno_is_a740_family(adreno_gpu)) >> + return; >> + >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS4_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS5_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS6_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS7_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 1000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS8_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS9_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 1000); > > https://lore.kernel.org/linux-arm-msm/002eb889-87cb-4b8c-98fb-6826c6977868@oss.qualcomm.com/ I missed the timeout value update. It is not bad since we already have the same value for TCS3 above. Will fix them all separately. -Akhil. > > Konrad