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Tue, 04 Oct 2022 14:41:14 +0000 Received: from NALASPPMTA02.qualcomm.com (NALASPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 294EfEL8022165; Tue, 4 Oct 2022 14:41:14 GMT Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (PPS) with ESMTPS id 294EfDS9022164 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Oct 2022 14:41:14 +0000 Received: from [10.111.163.178] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Tue, 4 Oct 2022 07:41:10 -0700 Message-ID: Date: Tue, 4 Oct 2022 07:41:09 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH 2/5] drm/msm/dsi: Remove repeated calculation of slice_per_intf Content-Language: en-US To: Marijn Suijten , , Rob Clark , Dmitry Baryshkov , Vinod Koul CC: <~postmarketos/upstreaming@lists.sr.ht>, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , David Airlie , Daniel Vetter , Sean Paul , Thomas Zimmermann , Javier Martinez Canillas , Alex Deucher , Douglas Anderson , Vladimir Lypak , , , , , Marek Vasut References: <20221001190807.358691-1-marijn.suijten@somainline.org> <20221001190807.358691-3-marijn.suijten@somainline.org> From: Abhinav Kumar In-Reply-To: <20221001190807.358691-3-marijn.suijten@somainline.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: DgDBxDrvdpKq74A7u0RsOO-jT0LGxUGa X-Proofpoint-GUID: DgDBxDrvdpKq74A7u0RsOO-jT0LGxUGa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-04_06,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 adultscore=0 clxscore=1015 suspectscore=0 mlxscore=0 mlxlogscore=999 impostorscore=0 spamscore=0 bulkscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210040095 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/1/2022 12:08 PM, Marijn Suijten wrote: > slice_per_intf is already computed for intf_width, which holds the same > value as hdisplay. > > Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration") > Signed-off-by: Marijn Suijten LGTM, Reviewed-by: Abhinav Kumar > --- > drivers/gpu/drm/msm/dsi/dsi_host.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c > index e05bae647431..cb6f2fa11f58 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c > @@ -842,7 +842,7 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, > static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay) > { > struct drm_dsc_config *dsc = msm_host->dsc; > - u32 reg, intf_width, reg_ctrl, reg_ctrl2; > + u32 reg, reg_ctrl, reg_ctrl2; > u32 slice_per_intf, total_bytes_per_intf; > u32 pkt_per_line; > u32 bytes_in_slice; > @@ -851,8 +851,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod > /* first calculate dsc parameters and then program > * compress mode registers > */ > - intf_width = hdisplay; > - slice_per_intf = DIV_ROUND_UP(intf_width, dsc->slice_width); > + slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width); > > /* If slice_per_pkt is greater than slice_per_intf > * then default to 1. This can happen during partial > @@ -861,7 +860,6 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod > if (slice_per_intf > dsc->slice_count) > dsc->slice_count = 1; > > - slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width); > bytes_in_slice = DIV_ROUND_UP(dsc->slice_width * dsc->bits_per_pixel, 8); > > dsc->slice_chunk_size = bytes_in_slice;