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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIyMDEyMyBTYWx0ZWRfX5kWA0cEN0QeM w6geAPGXVCqcGJ6XJPnLoxydZdvbAY3ZqOWJk2MUZqtp08Dg9lqZuRg9DXUztVs4eaI6j+Eb5ve M6iqPq1w0Eta+aKYCBES0Ywa3oxLb1UqMB5JQaKK3pdbnyu4DPLi9ctDiqTmHAi/xrAcvbrJBOc 1q66ugl9vlWsWCniAQypvC1u/60UjUrN67oBVE6aN8JEkTsnIYrTeVGFDw9dxAlD747XN0Lqg37 qYSDK4NtIYIAM/dCt2eJ0t4CLka1DCmjivahvDyApXTGhiPq3LiH7n/hFNwmYAepemMl6sHw3xF x/MvWgPouUUnSGSLMO06mxE4artqaKHyA4SvZplfSv3e5QG56C4a/N4RpBn/rfCprBASaV7zrEf 410ZVd0JnHrKo2wRrue+eGPX4JCme5grHzjk27q9kg/FFxwxgQgykCbRjXbIHMmKw9emLDhgbZP uZCfHBu6kFzqGtlemNA== X-Proofpoint-GUID: 1Upah3A0Y5DupsHQKsWkJNDcixjkAOM_ X-Authority-Analysis: v=2.4 cv=LNdWhpW9 c=1 sm=1 tr=0 ts=6a104b13 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=w2YRJOle7L1X8GQccsAA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-ORIG-GUID: 1Upah3A0Y5DupsHQKsWkJNDcixjkAOM_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-22_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605220123 On 5/14/26 6:13 AM, Varadarajan Narayanan wrote: > Add DT entries to enable the PCIe controllers found in ipq5210. > > Signed-off-by: Varadarajan Narayanan > --- [...] > &tlmm { > + pcie0_default_state: pcie0-default-state { > + pins = "gpio32"; > + function = "gpio"; > + drive-strength = <6>; > + bias-pull-down; > + output-low; > + }; > + > + pcie1_default_state: pcie1-default-state { > + pins = "gpio29"; > + function = "gpio"; > + drive-strength = <6>; > + bias-pull-down; > + output-low; You shouldn't need output-low in either of these definitions (+ sorting by GPIO idx would be extra neat) [...] > clocks { > + pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk { > + compatible = "fixed-clock"; > + clock-frequency = <250000000>; > + #clock-cells = <0>; > + }; > + > + pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk { > + compatible = "fixed-clock"; > + clock-frequency = <250000000>; > + #clock-cells = <0>; > + }; Why do these exist? Just pass the QMPPHY reference straight to GCC [...] > + pcie0_phy: phy@84000 { > + compatible = "qcom,ipq5210-qmp-gen3x1-pcie-phy", > + "qcom,ipq9574-qmp-gen3x1-pcie-phy"; > + reg = <0x0 0x00084000 0x0 0x1000>; > + > + clocks = <&gcc GCC_PCIE0_AUX_CLK>, > + <&gcc GCC_PCIE0_AHB_CLK>, > + <&gcc GCC_PCIE0_PIPE_CLK>; > + clock-names = "aux", "cfg_ahb", "pipe"; > + > + assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>; > + assigned-clock-rates = <20000000>; Is this clock supposed to be fixed at that rate, regardless of the link speed? And is the default rate incorrect? > + > + resets = <&gcc GCC_PCIE0_PHY_BCR>, > + <&gcc GCC_PCIE0PHY_PHY_BCR>; > + reset-names = "phy", "common"; > + > + #clock-cells = <0>; > + clock-output-names = "gcc_pcie0_pipe_clk_src"; Having a gcc_ prefix here smells fishy.. [...] > + clocks = <&gcc GCC_PCIE1_AXI_M_CLK>, > + <&gcc GCC_PCIE1_AXI_S_CLK>, > + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, > + <&gcc GCC_PCIE1_RCHNG_CLK>, > + <&gcc GCC_PCIE1_AHB_CLK>, > + <&gcc GCC_PCIE1_AUX_CLK>; > + > + clock-names = "axi_m", stray \n above, also in resets [...] > + pcie1_rp: pcie@0 { pcie1_port0 for consistency with other DTs, please Same comments for the other port Konrad