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Thu, 19 Feb 2026 01:53:27 -0800 (PST) X-Received: by 2002:a17:903:2390:b0:2aa:d327:beff with SMTP id d9443c01a7336-2ad5f701d04mr14625315ad.6.1771494806808; Thu, 19 Feb 2026 01:53:26 -0800 (PST) Received: from [10.92.198.80] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad1aadca84sm158860315ad.70.2026.02.19.01.53.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Feb 2026 01:53:26 -0800 (PST) Message-ID: Date: Thu, 19 Feb 2026 15:23:20 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] arm64: dts: qcom: sm8550: add OSM L3 node and cpu interconnect nodes To: Konrad Dybcio , webgeek1234@gmail.com, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Georgi Djakov , Sibi Sankar Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Taniya Das References: <20260218-sm8550-ddr-bw-scaling-v2-0-43a2b6d47e70@gmail.com> <20260218-sm8550-ddr-bw-scaling-v2-2-43a2b6d47e70@gmail.com> Content-Language: en-US From: Imran Shaik In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: H4L9qqVzCKKKV5zFvPLYct2URZ6JjRWS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE5MDA5MCBTYWx0ZWRfX6Q/h7ExKU34o VCdkHqk2qz2gwl3N6voyCAmCYhcUEEOcfPBchGDNvJqv27zZe2a22+/oX6sHo9maATa0Whk9H8c Yk3rqqM2dhzu9ZQ6AS3CEZDTQf/CdbC4utTLuYlnO4CRIG0ffTaFAGP7w5xtKZlMrJneTBalyVx GwpF2nv63QR3iz52IqRgSwIAE5Rp2E0PST3h2VNS1olZT9gXARNaskyjvOdCTFtkK/TLm/u0KKt wFLIttP0OiOy5dXaL9gTCeIasP32s+X0EFkGy0u8oVU+C6REBaQl9X7cTGpec8PVxlZV+jcljeI 2HkTw4owg8b8Uv7UXhp+KP/JDlBmhoy5Ayn5pjWo1GHFTl5ayEWZVBjm1VJQnZSshKeXXF3QDLe ExL4GK2Q+R4fnQYf2Tn6+NctcVY3Y38IJC9n4kdDjhu0fBEJQAEgriom1cQIcG8dyFktHp40DtU wqMxHmOD7Df6aihdUkA== X-Proofpoint-GUID: H4L9qqVzCKKKV5zFvPLYct2URZ6JjRWS X-Authority-Analysis: v=2.4 cv=daCNHHXe c=1 sm=1 tr=0 ts=6996dd98 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=VwQbUJbxAAAA:8 a=pGLkceISAAAA:8 a=ICX6NJ6XWj8aWO6CY-EA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-19_03,2026-02-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602190090 On 19-02-2026 02:59 pm, Konrad Dybcio wrote: > On 2/18/26 7:16 PM, Aaron Kling via B4 Relay wrote: >> From: Aaron Kling >> >> Add the OSC L3 Cache controller node. >> >> Also add the interconnect entry for each cpu, with 3 different paths: >> - CPU to Last Level Cache Controller (LLCC) >> - Last Level Cache Controller (LLCC) to DDR >> - L3 Cache from CPU to DDR interface >> >> Signed-off-by: Aaron Kling >> --- > > This should still be squashed with patch 3, as while you wire up the > CPUs as interconnect consumers, they cast no vote, leading to the > situation Krzysztof mentioned where the performance actually majorly > goes *down*, since the icc core sees no users present and assumes it can > send a zero-vote (which probably translates to F_MIN for the cache) > > Konrad > Yes, this is required to be squashed with patch 3. If only the interconnects are there, without opp-table support, then the cpufreq driver probe will fail while adding the opp table, due to mismatch between opp-peak-kBps and paths count. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/opp/of.c#n779 Thanks, Imran