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Say Y if you want S4 peripherals clock controller to work. >> + >> +config COMMON_CLK_T7_PLL >> + tristate "Amlogic T7 SoC PLL controller support" >> + depends on ARM64 >> + default y >> + select COMMON_CLK_MESON_REGMAP >> + select COMMON_CLK_MESON_CLKC_UTILS >> + select COMMON_CLK_MESON_PLL >> + imply COMMON_CLK_SCMI >> + help >> + Support for the PLL clock controller on Amlogic A311D2 based >> + device, AKA T7. PLLs are required by most peripheral to operate >> + Say Y if you are a T7 based device. >> + >> endmenu >> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile >> index bc56a47931c1..646257694c34 100644 >> --- a/drivers/clk/meson/Makefile >> +++ b/drivers/clk/meson/Makefile >> @@ -27,3 +27,4 @@ obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o >> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o >> obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o >> obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o >> +obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o >> diff --git a/drivers/clk/meson/t7-pll.c b/drivers/clk/meson/t7-pll.c >> new file mode 100644 >> index 000000000000..a6113b7dfe11 >> --- /dev/null >> +++ b/drivers/clk/meson/t7-pll.c >> @@ -0,0 +1,1193 @@ >> +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) >> +/* >> + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. >> + * Author: Jian Hu >> + */ >> + >> +#include >> +#include >> +#include "clk-regmap.h" >> +#include "clk-pll.h" >> +#include "clk-mpll.h" >> +#include "meson-clkc-utils.h" >> +#include "meson-eeclk.h" >> +#include >> + >> +#define ANACTRL_GP0PLL_CTRL0 0x00 >> +#define ANACTRL_GP0PLL_CTRL1 0x04 >> +#define ANACTRL_GP0PLL_CTRL2 0x08 >> +#define ANACTRL_GP0PLL_CTRL3 0x0c >> +#define ANACTRL_GP0PLL_CTRL4 0x10 >> +#define ANACTRL_GP0PLL_CTRL5 0x14 >> +#define ANACTRL_GP0PLL_CTRL6 0x18 >> +#define ANACTRL_GP0PLL_STS 0x1c >> + >> +#define ANACTRL_GP1PLL_CTRL0 0x00 >> +#define ANACTRL_GP1PLL_CTRL1 0x04 >> +#define ANACTRL_GP1PLL_CTRL2 0x08 >> +#define ANACTRL_GP1PLL_CTRL3 0x0c >> +#define ANACTRL_GP1PLL_STS 0x1c >> + >> +#define ANACTRL_HIFIPLL_CTRL0 0x00 >> +#define ANACTRL_HIFIPLL_CTRL1 0x04 >> +#define ANACTRL_HIFIPLL_CTRL2 0x08 >> +#define ANACTRL_HIFIPLL_CTRL3 0x0c >> +#define ANACTRL_HIFIPLL_CTRL4 0x10 >> +#define ANACTRL_HIFIPLL_CTRL5 0x14 >> +#define ANACTRL_HIFIPLL_CTRL6 0x18 >> +#define ANACTRL_HIFIPLL_STS 0x1c >> + >> +#define ANACTRL_PCIEPLL_CTRL0 0x00 >> +#define ANACTRL_PCIEPLL_CTRL1 0x04 >> +#define ANACTRL_PCIEPLL_CTRL2 0x08 >> +#define ANACTRL_PCIEPLL_CTRL3 0x0c >> +#define ANACTRL_PCIEPLL_CTRL4 0x10 >> +#define ANACTRL_PCIEPLL_CTRL5 0x14 >> +#define ANACTRL_PCIEPLL_STS 0x18 >> + >> +#define ANACTRL_MPLL_CTRL0 0x00 >> +#define ANACTRL_MPLL_CTRL1 0x04 >> +#define ANACTRL_MPLL_CTRL2 0x08 >> +#define ANACTRL_MPLL_CTRL3 0x0c >> +#define ANACTRL_MPLL_CTRL4 0x10 >> +#define ANACTRL_MPLL_CTRL5 0x14 >> +#define ANACTRL_MPLL_CTRL6 0x18 >> +#define ANACTRL_MPLL_CTRL7 0x1c >> +#define ANACTRL_MPLL_CTRL8 0x20 >> +#define ANACTRL_MPLL_STS 0x24 >> + >> +#define ANACTRL_HDMIPLL_CTRL0 0x00 >> +#define ANACTRL_HDMIPLL_CTRL1 0x04 >> +#define ANACTRL_HDMIPLL_CTRL2 0x08 >> +#define ANACTRL_HDMIPLL_CTRL3 0x0c >> +#define ANACTRL_HDMIPLL_CTRL4 0x10 >> +#define ANACTRL_HDMIPLL_CTRL5 0x14 >> +#define ANACTRL_HDMIPLL_CTRL6 0x18 >> +#define ANACTRL_HDMIPLL_STS 0x1c >> + >> +#define ANACTRL_MCLK_PLL_CNTL0 0x00 >> +#define ANACTRL_MCLK_PLL_CNTL1 0x04 >> +#define ANACTRL_MCLK_PLL_CNTL2 0x08 >> +#define ANACTRL_MCLK_PLL_CNTL3 0x0c >> +#define ANACTRL_MCLK_PLL_CNTL4 0x10 >> +#define ANACTRL_MCLK_PLL_STS 0x14 >> + >> +static const struct pll_mult_range media_pll_mult_range = { >> + .min = 125, >> + .max = 250, >> +}; > From now on I expect naming to be more predictable. > This is part of an ongoing clean-up to be able to more easily share > common part between SoC. The convention will be based on what's > the most the rest of drivers/clk/meson to minimize the alignnment diff > > In the general, clk names, ID name and variable as much as possible, > variables soc id prefixed Agreed with you. >> + >> +static const struct reg_sequence gp0_init_regs[] = { > t7_gp0_pll_init_regs Ok. > >> + { .reg = ANACTRL_GP0PLL_CTRL1, .def = 0x00000000 }, >> + { .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x00000000 }, >> + { .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 }, >> + { .reg = ANACTRL_GP0PLL_CTRL4, .def = 0x88770290 }, >> + { .reg = ANACTRL_GP0PLL_CTRL5, .def = 0x3927200a }, >> + { .reg = ANACTRL_GP0PLL_CTRL6, .def = 0x56540000 }, >> +}; >> + >> +static struct clk_regmap gp0_pll_dco = { > t7_gp0_pll_dco Ok. > >> + .data = &(struct meson_clk_pll_data){ >> + .en = { >> + .reg_off = ANACTRL_GP0PLL_CTRL0, >> + .shift = 28, >> + .width = 1, >> + }, >> + .m = { >> + .reg_off = ANACTRL_GP0PLL_CTRL0, >> + .shift = 0, >> + .width = 8, >> + }, >> + .n = { >> + .reg_off = ANACTRL_GP0PLL_CTRL0, >> + .shift = 10, >> + .width = 5, >> + }, >> + .l = { >> + .reg_off = ANACTRL_GP0PLL_STS, >> + .shift = 31, >> + .width = 1, >> + }, >> + .rst = { >> + .reg_off = ANACTRL_GP0PLL_CTRL0, >> + .shift = 29, >> + .width = 1, >> + }, >> + .range = &media_pll_mult_range, >> + .init_regs = gp0_init_regs, >> + .init_count = ARRAY_SIZE(gp0_init_regs), >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "gp0_pll_dco", >> + .ops = &meson_clk_pll_ops, >> + .parent_data = &(const struct clk_parent_data) { >> + .fw_name = "input", >> + }, >> + .num_parents = 1, >> + }, >> +}; >> + >> +static struct clk_regmap gp0_pll = { > t7_gp0_pll ... and so on. Ok, I will add t7_ prefix for the varibles and names. Also apply for t7-peripherals.c. >> + .data = &(struct clk_regmap_div_data){ >> + .offset = ANACTRL_GP0PLL_CTRL0, >> + .shift = 16, >> + .width = 3, >> + .flags = CLK_DIVIDER_POWER_OF_TWO, >> + }, >> + .hw.init = &(struct clk_init_data) { >> + .name = "gp0_pll", >> + .ops = &clk_regmap_divider_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &gp0_pll_dco.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> ...... >> + >> +static struct clk_hw *t7_gp0_hw_clks[] = { >> + [CLKID_GP0_PLL_DCO] = &gp0_pll_dco.hw, >> + [CLKID_GP0_PLL] = &gp0_pll.hw, >> +}; >> + >> +static struct clk_hw *t7_gp1_hw_clks[] = { >> + [CLKID_GP1_PLL_DCO] = &gp1_pll_dco.hw, >> + [CLKID_GP0_PLL] = &gp1_pll.hw, > ^ > This won't go well ... Ok,  I will fix it in next verion. > ...... > -- > Jerome