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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id d20-20020a2e3614000000b002a8d2c6300bsm5846704lja.48.2023.05.03.01.33.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 May 2023 01:33:16 -0700 (PDT) Message-ID: Date: Wed, 3 May 2023 11:33:16 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH 1/4] drm/msm/dsi: Adjust pclk rate for compression Content-Language: en-GB To: Jessica Zhang , Rob Clark , Abhinav Kumar , Sean Paul , David Airlie , Daniel Vetter , Marijn Suijten Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20230405-add-dsc-support-v1-0-6bc6f03ae735@quicinc.com> <20230405-add-dsc-support-v1-1-6bc6f03ae735@quicinc.com> From: Dmitry Baryshkov In-Reply-To: <20230405-add-dsc-support-v1-1-6bc6f03ae735@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 03/05/2023 04:19, Jessica Zhang wrote: > Divide the pclk rate by the compression ratio when DSC is enabled > > Signed-off-by: Jessica Zhang > --- > drivers/gpu/drm/msm/dsi/dsi_host.c | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c > index 43a5ec33eee8..35c69dbe5f6f 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c > @@ -561,7 +561,8 @@ void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) > clk_disable_unprepare(msm_host->byte_clk); > } > > -static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, bool is_bonded_dsi) > +static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, > + struct drm_dsc_config *dsc, bool is_bonded_dsi) > { > unsigned long pclk_rate; > > @@ -576,6 +577,11 @@ static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, bool > if (is_bonded_dsi) > pclk_rate /= 2; > > + /* If DSC is enabled, divide pclk by compression ratio */ > + if (dsc) > + pclk_rate = DIV_ROUND_UP(pclk_rate, > + dsc->bits_per_component * 3 / msm_dsc_get_bpp_int(dsc)); > + Don't we loose precision here? Would DIV_ROUND_UP(pclk_rate * bpp, dsc->bpc * 3) be better? > return pclk_rate; > } > > @@ -585,7 +591,7 @@ unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_d > struct msm_dsi_host *msm_host = to_msm_dsi_host(host); > u8 lanes = msm_host->lanes; > u32 bpp = dsi_get_bpp(msm_host->format); > - unsigned long pclk_rate = dsi_get_pclk_rate(mode, is_bonded_dsi); > + unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi); > u64 pclk_bpp = (u64)pclk_rate * bpp; > > if (lanes == 0) { > @@ -604,7 +610,7 @@ unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_d > > static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi) > { > - msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, is_bonded_dsi); > + msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi); > msm_host->byte_clk_rate = dsi_byte_clk_get_rate(&msm_host->base, is_bonded_dsi, > msm_host->mode); > > @@ -634,7 +640,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) > > dsi_calc_pclk(msm_host, is_bonded_dsi); > > - pclk_bpp = (u64)dsi_get_pclk_rate(msm_host->mode, is_bonded_dsi) * bpp; > + pclk_bpp = (u64)dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi) * bpp; > do_div(pclk_bpp, 8); > msm_host->src_clk_rate = pclk_bpp; > > -- With best wishes Dmitry