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([2600:8803:e7e4:1d00:d77b:6acc:2ad1:8ff]) by smtp.gmail.com with ESMTPSA id 5614622812f47-404d98060ecsm2154491b6e.27.2025.05.21.06.23.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 May 2025 06:23:16 -0700 (PDT) Message-ID: Date: Wed, 21 May 2025 08:23:14 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] pwm: axi-pwmgen: add support for external clock To: Krzysztof Kozlowski Cc: Michael Hennerich , =?UTF-8?Q?Nuno_S=C3=A1?= , Trevor Gamblin , =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250520-pwm-axi-pwmgen-add-external-clock-v1-0-6cd63cc001c8@baylibre.com> <20250520-pwm-axi-pwmgen-add-external-clock-v1-3-6cd63cc001c8@baylibre.com> <20250521-nostalgic-pretty-hedgehog-d08a77@kuoka> Content-Language: en-US From: David Lechner In-Reply-To: <20250521-nostalgic-pretty-hedgehog-d08a77@kuoka> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 5/21/25 5:10 AM, Krzysztof Kozlowski wrote: > On Tue, May 20, 2025 at 04:00:46PM GMT, David Lechner wrote: >> Add support for external clock to the AXI PWM generator driver. >> >> In most cases, there is a separate external clock that drives the PWM >> output separate from the peripheral clock. This allows enabling both >> clocks. >> >> Signed-off-by: David Lechner >> --- >> drivers/pwm/pwm-axi-pwmgen.c | 23 ++++++++++++++++++++--- >> 1 file changed, 20 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/pwm/pwm-axi-pwmgen.c b/drivers/pwm/pwm-axi-pwmgen.c >> index 4337c8f5acf055fc87dc134f2a70b99b0cb5ede6..67992a7561ec0440b1c1fa327f844a0602872771 100644 >> --- a/drivers/pwm/pwm-axi-pwmgen.c >> +++ b/drivers/pwm/pwm-axi-pwmgen.c >> @@ -280,9 +280,26 @@ static int axi_pwmgen_probe(struct platform_device *pdev) >> ddata = pwmchip_get_drvdata(chip); >> ddata->regmap = regmap; >> >> - clk = devm_clk_get_enabled(dev, NULL); >> - if (IS_ERR(clk)) >> - return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n"); >> + /* When clock-names is present, there is a separate ext clock. */ >> + if (device_property_present(dev, "clock-names")) { > > No. List is ordered, you do not need such dance at all. I should have added more to the comment here. This is also needed for backwards compatibility where only what should be the "ext" clock is given as clocks = <&spi_clk>; and the AXI clock was missing. > >> + struct clk *axi_clk; >> + >> + axi_clk = devm_clk_get_enabled(dev, "axi"); >> + if (IS_ERR(axi_clk)) >> + return dev_err_probe(dev, PTR_ERR(axi_clk), >> + "failed to get axi clock\n"); >> + >> + clk = devm_clk_get_enabled(dev, "ext"); > > So that's messing the order, which confirms my question from the > binding. > > No. List has a strict order, you cannot change it just because you want > to add optional clock. > > Best regards, > Krzysztof >