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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0efe490asm1890162166b.98.2025.01.03.05.14.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 03 Jan 2025 05:14:22 -0800 (PST) Message-ID: Date: Fri, 3 Jan 2025 14:14:19 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 7/8] arm64: dts: qcom: qcs8300: enable pcie1 for qcs8300 soc To: Ziyue Zhang , vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dmitry.baryshkov@linaro.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, andersson@kernel.org, konradybcio@kernel.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, quic_qianyu@quicinc.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com References: <20241220055239.2744024-1-quic_ziyuzhan@quicinc.com> <20241220055239.2744024-8-quic_ziyuzhan@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241220055239.2744024-8-quic_ziyuzhan@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: gHCE3jPXCZlaUk6iRaCObnmOIx3WhHpx X-Proofpoint-GUID: gHCE3jPXCZlaUk6iRaCObnmOIx3WhHpx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 mlxscore=0 malwarescore=0 suspectscore=0 mlxlogscore=566 spamscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501030116 On 20.12.2024 6:52 AM, Ziyue Zhang wrote: > Add configurations in devicetree for PCIe1, including registers, clocks, > interrupts and phy setting sequence. > > Signed-off-by: Ziyue Zhang > --- Acked-by: Konrad Dybcio Konrad