From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E49DECAAA1 for ; Thu, 27 Oct 2022 11:29:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235308AbiJ0L24 (ORCPT ); Thu, 27 Oct 2022 07:28:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233403AbiJ0L2x (ORCPT ); Thu, 27 Oct 2022 07:28:53 -0400 Received: from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com [66.111.4.25]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F12B10A7E1; Thu, 27 Oct 2022 04:28:52 -0700 (PDT) Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.nyi.internal (Postfix) with ESMTP id 367935C01D7; Thu, 27 Oct 2022 07:28:49 -0400 (EDT) Received: from imap51 ([10.202.2.101]) by compute3.internal (MEProxy); Thu, 27 Oct 2022 07:28:49 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arndb.de; h=cc :cc:content-type:date:date:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to; s=fm2; t=1666870129; x=1666956529; bh=IsY1kEvEYG Njx7tvNwuoNGkxDZVrFMwwBASmVJ2tn3o=; b=CkpnFEmGBwaVOTbhDV0IRXv7N7 xPFyaCGZDtG6ROD9CxdHqFKNgFkcYu2a4U3ZLQut2uYJQRwJ6ZGDhXJdWGAJrony nWAFG8zqZWsEBFG7F2GnCpjcNXC6JxaB9vjwZ+ABNGhfKU7gDUlwm2OqJb4dTpX1 Rig/fPMt1MY2hrBRnH8LYxCDm7uavciuYTlWZiBfQwQ6dcsV+LVJP7/gJvbpwz72 cMBrgRBPFXLnPtzBA7cmXRJTcwA9Ug5kC8B0gULeIa88FFEj7yVIA5Dk4IrOiGWp txnFA9yyIiKmQxh6402UdDtWOFMqm6gRBNyuyrMef22SIxdq4o9YRUAugv2Q== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-type:date:date:feedback-id :feedback-id:from:from:in-reply-to:in-reply-to:message-id :mime-version:references:reply-to:sender:subject:subject:to:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; t=1666870129; x=1666956529; bh=IsY1kEvEYGNjx7tvNwuoNGkxDZVr FMwwBASmVJ2tn3o=; b=Wle9Uf20LTzIbD/X59keL08he2hO5EH2lyhjIJ7Uxptl 05mCGIfVLtxLyRd4rUXyGEbQGt/ErY/+X9g9RNLiZzv6WAVMz3O2o674/jRGLq/C R2vlXDlAgMuGq0QgzFrLgrt1kxFpS3xlVUDnFFcNcWokWme9I6WONc587XjdSSOq /9IbswHm4kYSc+2dvGfWEatVLYyNbucUv1e66YgfdDT6aJmcKenQiwPVyZYTqOvi 1QqQ4i8w3R5ydx7ZPcZm8SBsUUt68oDKp2XPywLfMIwx2cEtAuuuwdeHY64xf4vr V+vL9CkEvXFdH8b1yt+8ZgVL2SgMiv+2EJub8t6XLA== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvgedrtdeggdefkecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefofgggkfgjfhffhffvvefutgesthdtredtreertdenucfhrhhomhepfdetrhhn ugcuuegvrhhgmhgrnhhnfdcuoegrrhhnugesrghrnhgusgdruggvqeenucggtffrrghtth gvrhhnpeffheeugeetiefhgeethfejgfdtuefggeejleehjeeutefhfeeggefhkedtkeet ffenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpegrrh hnugesrghrnhgusgdruggv X-ME-Proxy: Feedback-ID: i56a14606:Fastmail Received: by mailuser.nyi.internal (Postfix, from userid 501) id E5E92B60086; Thu, 27 Oct 2022 07:28:48 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.7.0-alpha0-1087-g968661d8e1-fm-20221021.001-g968661d8 Mime-Version: 1.0 Message-Id: In-Reply-To: <8c11d7c4-dfc4-b84c-82cd-a9708bd79aab@socionext.com> References: <20221027045157.23325-1-hayashi.kunihiko@socionext.com> <20221027045157.23325-5-hayashi.kunihiko@socionext.com> <8c11d7c4-dfc4-b84c-82cd-a9708bd79aab@socionext.com> Date: Thu, 27 Oct 2022 13:28:28 +0200 From: "Arnd Bergmann" To: "Kunihiko Hayashi" , "Rob Herring" , "Krzysztof Kozlowski" , "Olof Johansson" , "Masami Hiramatsu" Cc: soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 4/4] arm64: dts: uniphier: Add NX1 SoC and boards support Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 27, 2022, at 13:19, Kunihiko Hayashi wrote: > On 2022/10/27 19:01, Arnd Bergmann wrote: >> On Thu, Oct 27, 2022, at 06:51, Kunihiko Hayashi wrote: >>> + #interrupt-cells = <1>; >>> + interrupt-names = "dma", "msi"; >>> + interrupts = , >>> + ; >>> + interrupt-map-mask = <0 0 0 7>; >>> + interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ >>> + <0 0 0 2 &pcie_intc 1>, /* INTB */ >>> + <0 0 0 3 &pcie_intc 2>, /* INTC */ >>> + <0 0 0 4 &pcie_intc 3>; /* INTD */ >>> + phy-names = "pcie-phy"; >>> + phys = <&pcie_phy>; >>> + >>> + pcie_intc: legacy-interrupt-controller { >>> + interrupt-controller; >>> + #interrupt-cells = <1>; >>> + interrupt-parent = <&gic>; >>> + interrupts = > IRQ_TYPE_LEVEL_HIGH>; >>> + }; >>> + }; >> >> Shouldn't there be an "msi-map" or "msi-parent" property pointing at >> the GIC? > > Since Designware PCIe receives an interrupt from GIC with interrupt-name "msi" > and passes the interrupt to the linear irq domain corresponding to MSI, > I think there is neither "msi-map" nor "msi-parent" properties. Usually, you have the choice to use either the built-in MSI logic of the PCIe controller, or the one built into the GIC itself, assuming you have a modern enough GIC implemetation. Using the GIC is preferred here, because otherwise you lose all the benefits that MSIs offer, regarding latency and CPU affinity. Arnd