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([2001:b07:6468:f312:24d8:ed40:c82a:8a01]) by smtp.gmail.com with ESMTPSA id t5sm2922781wmi.34.2020.03.17.01.27.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Mar 2020 01:27:21 -0700 (PDT) Subject: Re: [PATCH] KVM: x86: Expose AVX512 VP2INTERSECT in cpuid for TGL To: Zhenyu Wang Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, "Zhong, Yang" References: <20200317065553.64790-1-zhenyuw@linux.intel.com> From: Paolo Bonzini Message-ID: Date: Tue, 17 Mar 2020 09:27:22 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <20200317065553.64790-1-zhenyuw@linux.intel.com> Content-Type: text/plain; charset=windows-1252 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17/03/20 07:55, Zhenyu Wang wrote: > On Tigerlake new AVX512 VP2INTERSECT feature is available. > This would expose it for KVM supported cpuid. > > Cc: "Zhong, Yang" > Signed-off-by: Zhenyu Wang > --- > arch/x86/kvm/cpuid.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index b1c469446b07..b4e25ff6ab0a 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -374,7 +374,7 @@ static inline void do_cpuid_7_mask(struct kvm_cpuid_entry2 *entry, int index) > const u32 kvm_cpuid_7_0_edx_x86_features = > F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | > F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | > - F(MD_CLEAR); > + F(MD_CLEAR) | F(AVX512_VP2INTERSECT); > > /* cpuid 7.1.eax */ > const u32 kvm_cpuid_7_1_eax_x86_features = > Hi Zhenyu, please rebase - the CPUID mechanism is completely rewritten in kvm/queue. Thanks, Paolo