From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Julien Stephan <jstephan@baylibre.com>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Matthias Brugger <matthias.bgg@gmail.com>,
Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>,
CK Hu <ck.hu@mediatek.com>
Cc: dri-devel@lists.freedesktop.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Tommy Chen <tommyyl.chen@mediatek.com>
Subject: Re: [PATCH] drm/mediatek: mtk_hdmi_v2: fix VID_DOWNSAMPLE_CONFIG register offset
Date: Mon, 14 Sep 2026 14:00:19 +0200 [thread overview]
Message-ID: <dcce7b12-edbd-4764-b154-ba178b74eb78@collabora.com> (raw)
In-Reply-To: <20260828-mtk-hdmi-v2-fix-register-offset-v1-1-118ad5d7ebe3@baylibre.com>
On 8/28/26 14:10, Julien Stephan wrote:
> According to the datasheet, VID_DOWNSAMPLE_CONFIG is at offset 0x8f0;
> 0x8d0 is the VID_CSC_COEFF_0 register.
>
> Fixes: 8d0f79886273 ("drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188")
> Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
prev parent reply other threads:[~2026-09-14 12:00 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-28 12:10 Julien Stephan
2026-09-03 9:04 ` Louis-Alexis Eyraud
2026-09-14 12:00 ` AngeloGioacchino Del Regno [this message]
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