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Fri, 26 Jun 2026 07:28:58 -0700 (PDT) X-Received: by 2002:a05:6102:148e:b0:6c2:7d0d:e09f with SMTP id ada2fe7eead31-73433e3675amr1248986137.1.1782484138384; Fri, 26 Jun 2026 07:28:58 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-697f4bd36adsm2993408a12.27.2026.06.26.07.28.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 26 Jun 2026 07:28:57 -0700 (PDT) Message-ID: Date: Fri, 26 Jun 2026 16:28:54 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v11 5/6] arm64: dts: qcom: monaco: Add OPP-table for ICE UFS and ICE eMMC nodes To: Abhinaba Rakshit Cc: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Adrian Hunter , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neeraj Soni , Harshal Dev , Kuldeep Singh , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org References: <20260609-enable-ice-clock-scaling-v11-0-1cebc8b3275b@oss.qualcomm.com> <20260609-enable-ice-clock-scaling-v11-5-1cebc8b3275b@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI2MDExOSBTYWx0ZWRfX20MxNmGxscyd XG9P5uZF0tzIprLRIzQYEww5BcbSQfomswjCBF+VocKZhqfkcTAwQnEo8zvhOavn3rpuq8amj+W A98A+rSVIF5vWkZWfWi0I5R0DCZ2fJ6CbLFkPlQGb0V79fROXPR82KA1Ec+J7pU3fgI6E25V3XT gKX/h1PpignoeX+Xsr+KNQ6Mym5fqKof8D5YlAzldChrSLit+XtgBez9+zujNG6D8BTcWt3aO3s yF+5BeXJAHJ8Thb06AQJtt0py1Vw4KFHYNVMKWHb3HCf99RfkPoGzgdgLKaR+QwfjPGMYth8c7S cEFmoaBnAWGWva/lv9nCAesdZbljYAcyWLViVn3WsaUNUGn9MQFmxoyoubXYr9KWLkEHIQOLWTM twR7SQljbbuH3topcKdNgXNUrxSXuqJqXOcipRwwBZY/5jP1M+J7ZyVdF6pwxWEnRgdgwhhXs53 djCT/ySGw1YKom+2Pxg== X-Authority-Analysis: v=2.4 cv=KNlqylFo c=1 sm=1 tr=0 ts=6a3e8cab cx=c_pps a=5HAIKLe1ejAbszaTRHs9Ug==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=wUXJofhvmvxpLSIlt_IA:9 a=QEXdDO2ut3YA:10 a=gYDTvv6II1OnSo0itH1n:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI2MDExOSBTYWx0ZWRfX0/vQG41fiEFc Yh/0zXyiSC/tm9T72magWdk+oqkL5jWmGDiXlpWe63YV4uDyK/cPabs8TK2CfTrLGrL/9YM8XGL J5uhUELODaoosFs9kCGtK/Bk526f+Qk= X-Proofpoint-ORIG-GUID: 36Uh4w1hvWdtthlYA-jAr5k65R1vC7X- X-Proofpoint-GUID: 36Uh4w1hvWdtthlYA-jAr5k65R1vC7X- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-26_03,2026-06-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 malwarescore=0 spamscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606260119 On 6/22/26 9:38 AM, Abhinaba Rakshit wrote: > On Thu, Jun 18, 2026 at 03:04:57PM +0200, Konrad Dybcio wrote: >> On 6/8/26 11:47 PM, Abhinaba Rakshit wrote: >>> Qualcomm Inline Crypto Engine (ICE) platform driver now, supports >>> an optional OPP-table. >>> >>> Add OPP-table for ICE UFS and ICE eMMC device nodes for Monaco >>> platform. >>> >>> Signed-off-by: Abhinaba Rakshit >>> --- >>> arch/arm64/boot/dts/qcom/monaco.dtsi | 37 ++++++++++++++++++++++++++++++++++++ >>> 1 file changed, 37 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi >>> index a1b6e6211b84d0d5008231c55613a0ccd61b9450..d9298d8b7874b8669b2cded2a28a99dce6eadbda 100644 >>> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi >>> @@ -2742,6 +2742,27 @@ ice: crypto@1d88000 { >>> clock-names = "core", >>> "iface"; >>> power-domains = <&gcc GCC_UFS_PHY_GDSC>; >>> + >>> + operating-points-v2 = <&ice_opp_table>; >>> + >>> + ice_opp_table: opp-table { >>> + compatible = "operating-points-v2"; >>> + >>> + opp-75000000 { >>> + opp-hz = /bits/ 64 <75000000>; >>> + required-opps = <&rpmhpd_opp_svs_l1>; >>> + }; >>> + >>> + opp-201600000 { >>> + opp-hz = /bits/ 64 <201600000>; >>> + required-opps = <&rpmhpd_opp_svs_l1>; >>> + }; >> >> Since 75 MHz and 201.6 Mhz require the same power level, is the former >> OPP any useful? > > Yes, both use the same power requirements. However recommended by the ICE team, > the DT should include all opp/freq supported by the hardware. Is there any reason at all where the OS would prefer the lower OPP? I think you at one point mentioned some dependency vs the storage controller's clock frequency Konrad