From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FD7F3D3CE4 for ; Tue, 21 Jul 2026 08:08:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784621338; cv=none; b=Xg/7J02UWbdDexadtWOD0aL+ENtDpP9HqK49ezu2YSzpfGThVQRYtgihSN4aio4PzjsB7aDTo269XIGpbWTDpec6LmegapKlw4qzHDDYxtyUahZhPmwHjypXgnhOIC3c5WoRVJ2oEfwM0/1cMCtiek1f2P8/cZYeK7arQuPCjVc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784621338; c=relaxed/simple; bh=UEUylPmzFnBo4UVGO9yk/CSuZKNdrB5NwZXwXC5qvL8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=teYRsJPqsmvBn1xIj27iRcCDeqeYz082icI/Vh2XQidkWOBYJy+pJ/nn7X6G45sgFTIGM9YrDfNkR9H/1Cx4X15ztmc+2cwCl4bIL9hDkvx5uM+Ta7saxqyzvSx0TFGCSYHzN2KJVJjMq0kzuMGUO3E6SZ+z6lyQ+ORdUk2wasM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AS7PrdBf; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AS7PrdBf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 775AF1F000E9; Tue, 21 Jul 2026 08:08:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784621337; bh=fVLDlt7OtdkiHRmNBt6TGjSGEaADwUAmP2pyF+NsbLs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=AS7PrdBf+DYtpFf1ipwrp8l8HJXglVR30KlrGXsw6kbYj4S+NaY2xNHoPse1wHJN4 HSpmWlpEnxQzRlTP9mfTaMRAE9zl6oDIcJ6yeNuRrYf0zL254FX8cJL2D6zTres0yj db1ur0GFa04gZXuI9sD0kvGodKDPKC36a0HvYIT6Of29lMIOABt7SM45sw4aZNBHan JABRrNeP+eTzu0ukMjtjlIgQXNxmamT9i/xCo47ea4Vw5VF0qPuLfe1nE1ewCYsA6q tQWJDhPKG9SpRVeZi175dDVf9WJbgqWzesJ4T/uf+f8faALt46Xr/QH+C1Jr+fNimB +FqJF0A7GLnJQ== From: "Naveen N Rao (AMD)" To: Borislav Petkov , Dave Hansen Cc: , , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , "H. Peter Anvin" , Thomas Gleixner Subject: [PATCH v3 1/3] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 Date: Tue, 21 Jul 2026 13:33:35 +0530 Message-ID: X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit For AMD family 0x10, EILVT offsets are not assigned by BIOS and is instead assigned by picking the next available EILVT offset. Use the maximum EILVT count for family 0x10 (APIC_EILVT_NR_AMD_10H) rather than an arbitrary maximum EILVT count when looking for the next available EILVT offset. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/events/amd/ibs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 3531f9c23b8c..555912ac520f 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1839,13 +1839,13 @@ static void force_ibs_eilvt_setup(void) preempt_disable(); /* find the next free available EILVT entry, skip offset 0 */ - for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) { + for (offset = 1; offset < APIC_EILVT_NR_AMD_10H; offset++) { if (get_eilvt(offset)) break; } preempt_enable(); - if (offset == APIC_EILVT_NR_MAX) { + if (offset == APIC_EILVT_NR_AMD_10H) { pr_debug("No EILVT entry available\n"); return; } -- 2.54.0