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Wed, 23 Aug 2023 08:25:59 GMT Received: from [10.217.198.224] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Wed, 23 Aug 2023 01:25:56 -0700 Message-ID: Date: Wed, 23 Aug 2023 13:55:53 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH v2] irqchip/qcom-pdc: add support for v3.2 HW Content-Language: en-US To: , Andy Gross , Bjorn Andersson , Konrad Dybcio , Thomas Gleixner , Marc Zyngier CC: , References: <20230822-topic-sm8x50-upstream-pdc-ver-v2-1-3035b8d388f7@linaro.org> <5d5ad774-3269-232a-db15-751726742460@quicinc.com> <543b1f3d-60b6-44fd-bddf-eb35cc163e10@linaro.org> From: "Maulik Shah (mkshah)" In-Reply-To: <543b1f3d-60b6-44fd-bddf-eb35cc163e10@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: UcN1_dw_aWnKY9423VQWx1YxiwGHUqsO X-Proofpoint-ORIG-GUID: UcN1_dw_aWnKY9423VQWx1YxiwGHUqsO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-23_06,2023-08-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 clxscore=1015 phishscore=0 suspectscore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308230076 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 8/23/2023 1:16 PM, Neil Armstrong wrote: > Hi, > > On 23/08/2023 07:35, Maulik Shah (mkshah) wrote: >> Hi Neil, >> >> @@ -142,8 +163,17 @@ static int qcom_pdc_gic_set_type(struct irq_data >> *d, unsigned int type) >>>           return -EINVAL; >>>       } >>> -    old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq); >>> -    pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type); >>> +    if (pdc_version < PDC_VERSION_3_2) { >>> +        old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq); >>> +        pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type); >>> +    } else { >>> +        u32 val; >>> + >>> +        val = pdc_reg_read(IRQ_i_CFG, d->hwirq); >>> +        old_pdc_type = val & IRQ_i_CFG_TYPE_MASK; >>> +        pdc_reg_write(IRQ_i_CFG, d->hwirq, >>> +                  pdc_type | (val & IRQ_i_CFG_IRQ_ENABLE)); >>> +    } >> While above is correct, i don't think we need version check in >> qcom_pdc_gic_set_type() as bits 0-2 are always for the type in >> old/new version as mentioned in v1. >> >> Adding one line after reading old_pdc_type should be good enough. > > Yes I understood, but while looking at the IRQ_i_CFG bits, I wanted to > keep the original > driver behavior intact by setting remaining bits to 0. > > Adding this single line changes that behavior and keeps bits 3-31 > to the default register value, which may have some consequences. > > If you consider it's an ok change, then I'll reduce it to this single > line. Yes this ok change to have single line and should not have  any consequences. Thanks, Maulik