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([2a01:e0a:106d:1080:aa0b:c7d:a032:4c3a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490bc3c183asm379335455e9.6.2026.06.08.01.23.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Jun 2026 01:23:37 -0700 (PDT) Message-ID: Date: Mon, 8 Jun 2026 10:23:36 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Reply-To: Neil Armstrong Subject: Re: [PATCH v2 0/3] ASoC: qcom: qdsp6: Add MI2S clock control To: Mohammad Rafi Shaik , Srinivas Kandagatla , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260608023011.942228-1-mohammad.rafi.shaik@oss.qualcomm.com> From: Neil Armstrong Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20260608023011.942228-1-mohammad.rafi.shaik@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 6/8/26 04:30, Mohammad Rafi Shaik wrote: > Add support for MI2S clock control within q6apm-lpass DAIs, including > handling of MCLK, BCLK, and ECLK via the DAI .set_sysclk callback. > Each MI2S port now retrieves its clock handles from the device tree, > allowing per-port clock configuration and proper enable/disable during > startup and shutdown. > > On platforms such as Monaco and Lemans, third-party codecs are > hardware-wired to the SoC and do not always have an in-tree codec > driver to manage their clocks. For these designs, clock line > enablement must be driven from the platform side, and this > series provides the necessary support for that. > > On QAIF-based platforms such as Shikra and Hawi, responsibility > for voting I2S MCLK and bit-clock has moved from the DSP to the > kernel. This series introduces the required device tree binding > support to represent and vote for these clocks from the kernel. > > Enhances the sc8280xp machine driver to set the boards spacific > configurations. > > This series depends on: > - https://lore.kernel.org/all/20260607-rubikpi-next-20260605-v1-3-7f334e16fea6@thundersoft.com/ > > --- > Changes in v3: > - Added a detailed commit description to clearly explain the need for this change. > - Improved the machine driver based on Neil’s feedback. > - Link to v1: https://lore.kernel.org/all/20260309111300.2484262-1-mohammad.rafi.shaik@oss.qualcomm.com/ > --- > Mohammad Rafi Shaik (3): > ASoC: dt-bindings: qcom,q6apm-lpass-dais: Document DAI subnode > ASoC: qcom: q6apm-lpass-dais: Add MI2S clock control > ASoC: qcom: sc8280xp: ASoC: qcom: sc8280xp: enhance machine driver for > board-specific config > > .../bindings/sound/qcom,q6apm-lpass-dais.yaml | 57 +++++ > sound/soc/qcom/qdsp6/q6apm-lpass-dais.c | 137 ++++++++++- > sound/soc/qcom/qdsp6/q6prm.h | 4 + > sound/soc/qcom/sc8280xp.c | 213 ++++++++++++++++-- > 4 files changed, 391 insertions(+), 20 deletions(-) > > > base-commit: 6e845bcb78c95af935094040bd4edc3c2b6dd784 > prerequisite-patch-id: 2f1bd3efac328030dd8efe28fb95f84603868043 Tested-by: Neil Armstrong # on SM8650-HDK With: ``` diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index eabc828c05b4..69327c4857e1 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -218,6 +218,22 @@ platform { sound-dai = <&q6apm>; }; }; + + pri-mi2s-dai-link { + link-name = "HDMI Playback"; + + cpu { + sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>; + }; + + codec { + sound-dai = <<9611_codec 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; }; vph_pwr: regulator-vph-pwr { @@ -853,6 +869,7 @@ &i2c6 { lt9611_codec: hdmi-bridge@2b { compatible = "lontium,lt9611uxc"; reg = <0x2b>; + #sound-dai-cells = <1>; interrupts-extended = <&tlmm 85 IRQ_TYPE_EDGE_FALLING>; @@ -861,7 +878,10 @@ lt9611_codec: hdmi-bridge@2b { vdd-supply = <<9611_1v2>; vcc-supply = <<9611_3v3>; - pinctrl-0 = <<9611_irq_pin>, <<9611_rst_pin>; + pinctrl-0 = <<9611_irq_pin>, + <<9611_rst_pin>, + <&i2s0_default_state>, + <&audio_mclk0_default_state>; pinctrl-names = "default"; ports { @@ -1072,6 +1092,19 @@ &pon_resin { status = "okay"; }; +&q6apmbedai { + #address-cells = <1>; + #size-cells = <0>; + + dai@16 { + reg = ; + clocks = <&q6prmcc LPASS_CLK_ID_MCLK_1 LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_PRI_MI2S_IBIT LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", + "bclk"; + }; +}; + &qup_i2c3_data_clk { /* Use internal I2C pull-up */ bias-pull-up = <2200>; diff --git a/sound/soc/qcom/sc8280xp.c b/sound/soc/qcom/sc8280xp.c index 1f3afc6d015c..7b34ff533e0d 100644 --- a/sound/soc/qcom/sc8280xp.c +++ b/sound/soc/qcom/sc8280xp.c @@ -320,18 +320,36 @@ static struct snd_soc_common sm8450_priv_data = { .driver_name = "sm8450", .dapm_widgets = sc8280xp_dapm_widgets, .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets), + /* I2S Connected to HDMI */ + .mi2s_mclk_enable = true, + .mi2s_bclk_enable = true, + .codec_dai_fmt = SND_SOC_DAIFMT_BC_FC | + SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_I2S, }; static struct snd_soc_common sm8550_priv_data = { .driver_name = "sm8550", .dapm_widgets = sc8280xp_dapm_widgets, .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets), + /* I2S Connected to HDMI */ + .mi2s_mclk_enable = true, + .mi2s_bclk_enable = true, + .codec_dai_fmt = SND_SOC_DAIFMT_BC_FC | + SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_I2S, }; static struct snd_soc_common sm8650_priv_data = { .driver_name = "sm8650", .dapm_widgets = sc8280xp_dapm_widgets, .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets), + /* I2S Connected to HDMI */ + .mi2s_mclk_enable = true, + .mi2s_bclk_enable = true, + .codec_dai_fmt = SND_SOC_DAIFMT_BC_FC | + SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_I2S, }; static struct snd_soc_common sm8750_priv_data = { ``` Thanks, Neil