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From: Mark Brown <broonie@kernel.org>
To: Vladimir Oltean <vladimir.oltean@nxp.com>
Cc: James Clark <james.clark@linaro.org>,
	Vladimir Oltean <olteanv@gmail.com>,
	Arnd Bergmann <arnd@arndb.de>,
	Larisa Grigore <larisa.grigore@nxp.com>,
	Frank Li <Frank.li@nxp.com>, Christoph Hellwig <hch@lst.de>,
	linux-spi@vger.kernel.org, imx@lists.linux.dev,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 0/6] spi: spi-fsl-dspi: Target mode improvements
Date: Tue, 1 Jul 2025 16:16:50 +0100	[thread overview]
Message-ID: <dd41f014-79e8-4567-9617-754b93e2c12d@sirena.org.uk> (raw)
In-Reply-To: <20250701145312.zx56ji4vvaoxwzkc@skbuf>

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On Tue, Jul 01, 2025 at 05:53:12PM +0300, Vladimir Oltean wrote:

> I suppose one could try using FIFO mode for transfers which request
> timestamping and DMA for transfers which don't. I don't have an insight
> into what impact that will have on the driver, but I suspect at the very
> least one will have to transform "DSPI_DMA_MODE" into "dspi->dma_available"
> and "dspi->dma_in_use", and reconfigure the SPI_RSER register (interrupt
> routing, to DMA engine or to CPUs) at every transfer rather than at dspi_init().

> The question is whether you would be willing to see and maintain such
> complexity increase, when AFAIK, the LS1028A FIFO mode passes its
> requirements.

Switching between modes is incredibly common, usually between PIO (for
very short transfers) and DMA, that's no problem.  Factoring in
timestamping seems like a reasonable signal I guess, might trip someone
who was trying to benchmark things up but probably not normal users.

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  reply	other threads:[~2025-07-01 15:16 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-27 10:21 James Clark
2025-06-27 10:21 ` [PATCH v4 1/6] spi: spi-fsl-dspi: Clear completion counter before initiating transfer James Clark
2025-06-27 19:41   ` Frank Li
2025-06-27 10:21 ` [PATCH v4 2/6] spi: spi-fsl-dspi: Store status directly in cur_msg->status James Clark
2025-06-27 21:30   ` Vladimir Oltean
2025-06-30 12:54     ` James Clark
2025-06-30 20:41       ` Vladimir Oltean
2025-07-01 10:02         ` James Clark
2025-07-21 13:25     ` James Clark
2025-07-21 13:39       ` Vladimir Oltean
2025-07-21 14:02         ` James Clark
2025-07-21 14:04           ` Mark Brown
2025-06-27 10:21 ` [PATCH v4 3/6] spi: spi-fsl-dspi: Stub out DMA functions James Clark
2025-06-27 10:21 ` [PATCH v4 4/6] spi: spi-fsl-dspi: Use non-coherent memory for DMA James Clark
2025-06-27 19:38   ` Frank Li
2025-06-27 10:21 ` [PATCH v4 5/6] spi: spi-fsl-dspi: Increase DMA buffer size James Clark
2025-06-27 19:44   ` Frank Li
2025-06-30  8:59     ` James Clark
2025-07-01 14:47   ` Vladimir Oltean
2025-07-01 15:08     ` James Clark
2025-07-01 15:09     ` Arnd Bergmann
2025-06-27 10:21 ` [PATCH v4 6/6] spi: spi-fsl-dspi: Report FIFO overflows as errors James Clark
2025-06-27 19:56   ` Frank Li
2025-06-27 21:41     ` Mark Brown
2025-06-30 10:46       ` James Clark
2025-06-30 11:40 ` (subset) [PATCH v4 0/6] spi: spi-fsl-dspi: Target mode improvements Mark Brown
2025-06-30 15:26 ` Vladimir Oltean
2025-07-01 12:42   ` James Clark
2025-07-01 13:18     ` Mark Brown
2025-07-01 13:57     ` Vladimir Oltean
2025-07-01 14:36       ` Mark Brown
2025-07-01 14:53         ` Vladimir Oltean
2025-07-01 15:16           ` Mark Brown [this message]
2025-07-01 15:24             ` Vladimir Oltean
2025-07-01 15:30               ` Mark Brown

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