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Sun, 03 May 2026 20:37:39 -0700 (PDT) X-Received: by 2002:a05:6a00:bd84:b0:82f:39df:dd54 with SMTP id d2e1a72fcca58-834fff00167mr13681818b3a.8.1777865858697; Sun, 03 May 2026 20:37:38 -0700 (PDT) Received: from [10.92.193.136] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-835158bcb99sm11045688b3a.25.2026.05.03.20.37.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 03 May 2026 20:37:38 -0700 (PDT) Message-ID: Date: Mon, 4 May 2026 09:07:31 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: PCI: qcom: Add D3cold support To: Steev Klimaszewski Cc: bhelgaas@google.com, bjorn.andersson@oss.qualcomm.com, jingoohan1@gmail.com, jonathanh@nvidia.com, kwilczynski@kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, mani@kernel.org, robh@kernel.org, will@kernel.org References: <20260429-d3cold-v5-0-89e9735b9df6@oss.qualcomm.com> <20260503203008.287559-1-threeway@gmail.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20260503203008.287559-1-threeway@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: GzZH1eNhneewSPHsQthfWbuzXiPvs3e6 X-Proofpoint-GUID: GzZH1eNhneewSPHsQthfWbuzXiPvs3e6 X-Authority-Analysis: v=2.4 cv=QY5WeMbv c=1 sm=1 tr=0 ts=69f81484 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=wWH99FW7VD-f-Ch3qS4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA0MDAzNCBTYWx0ZWRfX0l/lA6mEdFGO HlrGiKC+g1OsyaUFtjAziQz12Fbf98/qpQ7GfRs2h5zjINTYdWdz5zyFBV1NMKUDGh9v0yBCqlQ TiIN1t+YvQ260bBCkafkzKQJRFuModlusPFDmi0q2uWAMkAlcAPg+G+KChQsp+2BPPctMEtKuHv JamWUuK2oldofdDVgo06XgTUnwk2R2ZsPrJAa2vJakczW/WdCoWnAayb1VjLzCF438LVhoEZBfm cb4Clcaqepyh0n20CXWZxFEXjBBLAPg9sTRgJprLjzjtf5UI8uondrSmWaEZOCgLxl3Qob4hpK6 ewpmzI5hyxCfxu9RsikgyGzhCgF4kIq9wlZwRyMSNqw9LN7XMyp7h8Ot43wDkYYmDVodZHyd++O yUOtRteA56gkd7VZt297liJ9IE5/gtuUewIpsrnzLDKbgrBsFlBdvHI5XRVkYIBUTc1eTsN097C h666ANHZXrF10+zGVaQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-04_01,2026-04-30_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 adultscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605040034 On 5/4/2026 2:00 AM, Steev Klimaszewski wrote: > Hi Krishna, > >> This series adds support for putting Qualcomm PCIe host bridges into D3cold >> when downstream conditions allow it, and introduces a small common helper >> to determine D3cold eligibility based on endpoint state. >> On Qualcomm platforms, PCIe host controllers are currently kept powered >> even when there are no active endpoints (i.e. all endpoints are already in >> PCI_D3hot). This prevents the SoC from entering deeper low‑power states >> such as CXPC. >> While PCIe D3cold support exists in the PCI core, host controller drivers >> lack a common mechanism to determine whether it is safe to power off the >> host bridge without breaking active devices or wakeup functionality. >> As a result, controllers either avoid entering D3cold or depend on rough, >> driver‑specific workarounds. >> This series addresses that gap. >> 1. Introduces pci_host_common_can_enter_d3cold(), a helper that determines >> whether a host bridge may enter D3cold based on downstream PCIe endpoint >> state. The helper permits D3cold only when all *active* endpoints are >> already in PCI_D3hot, and any wakeup‑enabled endpoint supports PME >> from D3cold. >> 2. Updates the Designware PCIe host driver to use this helper in the >> suspend_noirq() path, replacing the existing heuristic that blocked >> D3cold whenever L1 ASPM was enabled. >> 3. Enables D3cold support for Qualcomm PCIe controllers by wiring them into >> the DesignWare common suspend/resume flow and explicitly powering down >> controller resources when all endpoints are in D3hot. >> The immediate outcome of this series is that Qualcomm PCIe host bridges can >> enter D3cold when all endpoints are in D3hot. >> This is a necessary but not sufficient step toward unblocking CXPC. With >> this series applied, CXPC can be achieved on systems with no attached NVMe >> devices. Support for NVMe‑attached systems requires additional changes >> in NVMe driver, which are being worked on separately. >> Tested on: >> - Qualcomm Lemans EVK, Monaco & sc7280 platforms. >> Validation steps: >> - Boot without NVMe attach: >> * PCIe host enters D3cold during suspend >> * SoC is able to reach CXPC provided other drivers also remove >> their votes as part of suspend. > I have been testing this patchset with Mani's patchset that is supposed to be > related to NVMe on the Thinkpad X13s found at: > > https://lore.kernel.org/all/20260414-l1ss-fix-v1-0-adbb4555b5ab@oss.qualcomm.com/ > > v4 of this patchset *boots* along with Mani's patchset, however, v5 does not, > and unfortunately, the machine does not seem to get to a point where I can even > get logs from it. Do you know what I might be missing? I have *not* attempted > to remove the nvme drive and boot off USB to test it. This series, will not have any impact on the boot, this series comes in to the picture only in case of suspend and resume. can you share your platform details and kernel you are booting with. - Krishna Chaitanya. > > -- steev