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Wed, 11 Nov 2026 11:21:29 -0800 (PST) Received: from [10.67.48.245] ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b197c42a4csm596583a91.4.2026.11.11.11.21.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Nov 2026 11:21:28 -0800 (PST) Message-ID: Date: Wed, 11 Nov 2026 11:21:27 -0800 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] clk: ingenic: Poll JZ4780 CPU1 power status atomically To: Brian Masney Cc: linux-mips@vger.kernel.org, Paul Cercueil , Thomas Bogendoerfer , Paul Burton , Stephen Boyd , Brian Masney , Jerome Brunet , =?UTF-8?B?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= , Jiaxun Yang , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, hns@goldelico.com, paul@boddie.org.uk References: <20261110043131.1985993-1-f.fainelli@gmail.com> <20261110043131.1985993-2-f.fainelli@gmail.com> <179442247882.1131744.13316822371180932611.b4-review@b4> Content-Language: en-US, fr-FR From: Florian Fainelli In-Reply-To: <179442247882.1131744.13316822371180932611.b4-review@b4> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 11/11/26 10:41, Brian Masney wrote: > Hi Florian, > >> The CPU1 clock enable callback runs under the clock framework's spinlock >> with interrupts disabled. Its readl_poll_timeout() can sleep between >> reads, which is invalid in this context when SMP powers up CPU1. >> >> Use readl_poll_timeout_atomic() with the existing interval and timeout. >> This is a prerequisite for the JZ4780 SMP bring-up path. The original >> CPU1 clock implementation by Zhou Yanjie is already upstream. >> >> Cross-built for CI20; the subsequent SMP-enabled image brought up both >> CPU cores. Development and validation used Codex assistance. >> >> Fixes: 6673db4f3f26 ("clk: JZ4780: Add function for enable the second core.") >> Link: https://lkml.kernel.org/r/1582215889-113034-3-git-send-email-zhouyanjie@wanyeetech.com > > Cc: stable OK, I will add that, thanks! > >> Reviewed-by: Paul Cercueil >> Signed-off-by: Florian Fainelli >> --- >> drivers/clk/ingenic/jz4780-cgu.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c >> index 1e88aef7ac0f..f5983033583a 100644 >> --- a/drivers/clk/ingenic/jz4780-cgu.c >> +++ b/drivers/clk/ingenic/jz4780-cgu.c >> @@ -242,7 +242,7 @@ static int jz4780_core1_enable(struct clk_hw *hw) >> spin_unlock_irqrestore(&cgu->lock, flags); >> >> /* wait for the CPU to be powered up */ >> - retval = readl_poll_timeout(cgu->base + CGU_REG_LCR, lcr, >> + retval = readl_poll_timeout_atomic(cgu->base + CGU_REG_LCR, lcr, >> !(lcr & LCR_SCPUS), 10, timeout); > > Since you are making changes here, please fix the alignment of the > next line with (. Certainly, will submit a newer version shortly. -- Florian