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Tue, 29 Apr 2025 22:54:16 -0700 (PDT) Received: from [192.168.68.51] ([180.233.125.65]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74039a94aecsm792360b3a.178.2025.04.29.22.54.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Apr 2025 22:54:16 -0700 (PDT) Message-ID: Date: Wed, 30 Apr 2025 15:54:08 +1000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 12/43] KVM: arm64: vgic: Provide helper for number of list registers To: Steven Price , kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" References: <20250416134208.383984-1-steven.price@arm.com> <20250416134208.383984-13-steven.price@arm.com> Content-Language: en-US From: Gavin Shan In-Reply-To: <20250416134208.383984-13-steven.price@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 4/16/25 11:41 PM, Steven Price wrote: > Currently the number of list registers available is stored in a global > (kvm_vgic_global_state.nr_lr). With Arm CCA the RMM is permitted to > reserve list registers for its own use and so the number of available > list registers can be fewer for a realm VM. Provide a wrapper function > to fetch the global in preparation for restricting nr_lr when dealing > with a realm VM. > > Signed-off-by: Steven Price > --- > New patch for v6 > --- > arch/arm64/kvm/vgic/vgic.c | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) > With below nitpick addressed: Reviewed-by: Gavin Shan > diff --git a/arch/arm64/kvm/vgic/vgic.c b/arch/arm64/kvm/vgic/vgic.c > index 8f8096d48925..8d189ce18ea0 100644 > --- a/arch/arm64/kvm/vgic/vgic.c > +++ b/arch/arm64/kvm/vgic/vgic.c > @@ -21,6 +21,11 @@ struct vgic_global kvm_vgic_global_state __ro_after_init = { > .gicv3_cpuif = STATIC_KEY_FALSE_INIT, > }; > > +static inline int kvm_vcpu_vgic_nr_lr(struct kvm_vcpu *vcpu) > +{ > + return kvm_vgic_global_state.nr_lr; > +} > + > /* > * Locking order is always: > * kvm->lock (mutex) > @@ -802,7 +807,7 @@ static void vgic_flush_lr_state(struct kvm_vcpu *vcpu) > lockdep_assert_held(&vgic_cpu->ap_list_lock); > > count = compute_ap_list_depth(vcpu, &multi_sgi); > - if (count > kvm_vgic_global_state.nr_lr || multi_sgi) > + if (count > kvm_vcpu_vgic_nr_lr(vcpu) || multi_sgi) > vgic_sort_ap_list(vcpu); > > count = 0; > @@ -831,7 +836,7 @@ static void vgic_flush_lr_state(struct kvm_vcpu *vcpu) > > raw_spin_unlock(&irq->irq_lock); > > - if (count == kvm_vgic_global_state.nr_lr) { > + if (count == kvm_vcpu_vgic_nr_lr(vcpu)) { > if (!list_is_last(&irq->ap_list, > &vgic_cpu->ap_list_head)) > vgic_set_underflow(vcpu); > @@ -840,7 +845,7 @@ static void vgic_flush_lr_state(struct kvm_vcpu *vcpu) > } > > /* Nuke remaining LRs */ > - for (i = count ; i < kvm_vgic_global_state.nr_lr; i++) > + for (i = count ; i < kvm_vcpu_vgic_nr_lr(vcpu); i++) > vgic_clear_lr(vcpu, i); > The unnecessary space before the semicolon can be dropped. for (i = count; i < kvm_vcpu_vgic_nr_lr(vcpu); i++) > if (!static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) Thanks, Gavin