From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DE1E4825A8; Thu, 10 Sep 2026 12:01:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789041674; cv=none; b=dXu0MTJ2WeXflpyHflQj6KzevOIZgYsWfTue1fxCBmlBeRCndFZq1xporWDHWrA0VWPrAMEJBx57m0v8aal1jdAmHnm31BgxFzoR1JEgdKoKzmYtsrJhZzc9FKm0gkz9QnBb1Ux5cgv+VO2bUDisEKiyOhgvji14r+1KCgv1P3k= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789041674; c=relaxed/simple; bh=EiLR1oNWBTUfzhayliGRuhK28Eyt3bB++mx+A/XcLOA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=DcIYDLr/DRAS0Tkr2w2joZBTyY7xkfu7XFx37oQCeogx6SlElYC+Mp9expgPEhBavaBt5xGeJv6Q94zEBEGy2ERFbcVgtjQW/7uwcjDK64fztPindAM79CCaB4EhrAnwqBxdH3KLCVcnX/gJ/SsPq33kdBZk5dRFRjQbQ+g7waw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FhEat1/v; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FhEat1/v" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C017C1F000FF; Thu, 10 Sep 2026 12:01:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1789041672; bh=gGRiP00UZ2QnxQeyHEnzHM+4PwMNnzfPUpjThhppjiI=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=FhEat1/vifu+AabmjF8NmJPEP65qR4NBg4Ky/6jU3lo17Q0Zo2BhNylfwMKgXlIDI UMImBV5640D83WmIILt73l8RjBygDF6Mt7gu1/ntqS0oBR8lidQsw7r3Sj2i5WdR8V INjCSwvtzlHK8kPH7G5nIBuVR3YVGY4ybJh+g5gGSFGtxyX6EYVptvqJMZZwjeQfGi aeG04jNaLuKWedKy71l1HWQfVdwcFptEjzJJ89C6fdNfHpJadbzrMhFXlVUL2CJHgj w8mBMnWhfb9D+zFJggWb28AQFcd5s8vG8Yuhm57TZx5ehR5Gfv4Ij2Aijxv4bMLNbQ hZcM2Ic2G/G5A== Message-ID: Date: Thu, 10 Sep 2026 14:01:02 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 07/26] mm/fbatch: LRU_NEXT_ACTIVATE bit to optimize folio_activate() Content-Language: en-US To: Hugh Dickins , Andrew Morton Cc: Ackerley Tng , Alexander Viro , Alexandre Ghiti , Baolin Wang , Barry Song , Binbin Wu , Christian Brauner , Christoph Hellwig , Christoph Lameter , Claudio Imbrenda , David Hildenbrand , JP Kobryn , Jan Kara , Jens Axboe , Johannes Weiner , Kairui Song , Kiryl Shutsemau , Lance Yang , Leonardo Bras , Lorenzo Stoakes , Marcelo Tosatti , Matthew Wilcox , Mel Gorman , Miaohe Lin , Michal Hocko , Minchan Kim , Muchun Song , Oscar Salvador , Peter Zijlstra , Qi Zheng , Rik van Riel , Sebastian Andrzej Siewior , Shakeel Butt , Suren Baghdasaryan , Yang Shi , Yu Zhao , Zach O'Keefe , Zi Yan , linux-block@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org References: From: "Vlastimil Babka (SUSE)" Autocrypt: addr=vbabka@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 9/9/26 11:55, Hugh Dickins wrote: > Implement an equivalent to the old __lru_cache_activate_folio() > optimization, to activate a folio recently put in the lru_add fbatch, > without having to put it through the lru_activate fbatch too. Neither > lruvec lock nor lru bit can guard this safely and efficiently, so resort > to try_cmpxchg() on a further, LRU_NEXT_ACTIVATE bit in folio->lru_next. > > Signed-off-by: Hugh Dickins > --- > include/linux/mm_inline.h | 4 ++++ > mm/folio.c | 23 ++++++++++++++++++++--- > 2 files changed, 24 insertions(+), 3 deletions(-) > > diff --git a/include/linux/mm_inline.h b/include/linux/mm_inline.h > index 8420b1276535..8f5efadf9c7c 100644 > --- a/include/linux/mm_inline.h > +++ b/include/linux/mm_inline.h > @@ -346,6 +346,7 @@ static inline void folio_migrate_refs(struct folio *new, const struct folio *old > enum { > LRU_NEXT_NEVER_TAIL = 0, /* Used by a tail's compound_head */ > LRU_NEXT_BATCHED = 1, /* Not used by any aligned pointer */ > + LRU_NEXT_ACTIVATE, > NR_LRU_NEXT_FLAGS > }; This addition, and the comment "/* This mask will do nothing on 64-bit */" in folio_add_lru()... does it mean that now this is breaking 32-bit? Should we make this optimization, or perhaps all of the cpu fbatch, 64-bit only? > @@ -358,6 +359,9 @@ bool lru_add_del_folio(struct folio *folio) > if (!(lru_next & BIT(LRU_NEXT_BATCHED))) > return false; > > + if (lru_next & BIT(LRU_NEXT_ACTIVATE)) > + folio_set_active(folio); > + > WRITE_ONCE(folio->lru.next, LIST_POISON1); > /* BUG_ON(folio->lru_next & BIT(LRU_NEXT_BATCHED)); */ > > diff --git a/mm/folio.c b/mm/folio.c > index a18d8ef6afd5..0b75c3b69d5a 100644 > --- a/mm/folio.c > +++ b/mm/folio.c > @@ -256,15 +256,32 @@ static void lru_activate(struct lruvec *lruvec, struct folio *folio) > > void folio_activate(struct folio *folio) > { > + unsigned long lru_next; > + > if (folio_test_active(folio) || folio_test_unevictable(folio) || > !folio_test_lru(folio)) > return; > > /* > - * XXX: It is curiously difficult to recreate safely the old > - * __lru_cache_activate_folio() optimization (folio_set_active() > - * directly if it's on the local lru_add fbatch): revisit later. > + * This optimization is intended for the common case of folio > + * having been recently added to this CPU's lru_add fbatch. > + * But since other CPUs can now take it at any instant (after > + * a folio_test_clear_lru()), and we may be migrated to another > + * CPU, it is simplest just to extend the optimization to all CPUs. > + * > + * folio_set_active() would be unsafe without the lruvec lock, and > + * a folio_test_clear_lru() here might cause a racing drain of the > + * lru_add fbatch to skip its lru_add(): so use try_cmpxchg(). > */ > + lru_next = READ_ONCE(folio->lru_next); > + while (lru_next & BIT(LRU_NEXT_BATCHED)) { > + if (lru_next & BIT(LRU_NEXT_ACTIVATE)) > + return; > + if (try_cmpxchg(&folio->lru_next, &lru_next, > + lru_next | BIT(LRU_NEXT_ACTIVATE))) > + return; > + } > + > folio_batch_add_and_move(folio, lru_activate); > } >