Re: [PATCH] arm64: Add kernel parameter to disable trap EL0 accesses to IMPDEF regs

["Liao, Chang" <liaochang1@huawei.com>]

Hi, Yicong

在 2025/10/22 13:26, Yicong Yang 写道:
> On 2025/10/21 19:54, Liao Chang wrote:
>> Add kernel parameter to allow system-wide EL0 access to IMPDEF system
>> regregisters and instructions without trapping to EL1/EL2. Since trap
>> overhead will compromises benefits, and it's even worse in
>> virtualization on CPU where certain IMPDEF registers and instructions
>> are designed for EL0 performance use.
>>
>> More early discussion could be found from link below.
>>
>> Link: https://lore.kernel.org/all/24afb8de-622a-4865-bd8e-8e89ccfff8f4@huawei.com/
>> Tested-by: Xinyu Zheng <zhengxinyu6@huawei.com>
>> Signed-off-by: Liao Chang <liaochang1@huawei.com>
>> ---
>>  Documentation/admin-guide/kernel-parameters.txt |  9 +++++++++
>>  arch/arm64/kernel/cpufeature.c                  | 14 +++++++++++++-
>>  2 files changed, 22 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
>> index 5a7a83c411e9..11ffa9f7b972 100644
>> --- a/Documentation/admin-guide/kernel-parameters.txt
>> +++ b/Documentation/admin-guide/kernel-parameters.txt
>> @@ -326,6 +326,15 @@
>>  			See Documentation/arch/arm64/asymmetric-32bit.rst for more
>>  			information.
>>  
>> +	no_trap_el0_impdef [Arm64,EARLY]
>> +			Allow system-wide EL0 access to IMPDEF system registers
>> +			and instructions without trapping to EL1/EL2.
>> +			Since trap overhead compromises benefits, and it's even
>> +			worse in virtualization on CPU where certain IMPDEF
>> +			registers and instructions are designed for EL0
>> +			performance use. This assumes the kernel adds the
>> +			support for Armv8.8 extension FEAT_TIDCP1.
>> +
>>  	amd_iommu=	[HW,X86-64]
>>  			Pass parameters to the AMD IOMMU driver in the system.
>>  			Possible values are:
>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index ef269a5a37e1..d12e35d799ee 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -2459,9 +2459,21 @@ static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, in
>>  }
>>  #endif /* CONFIG_KVM */
>>  
>> +static bool no_trap_el0_impdef;
>> +
>> +static int __init parse_no_trap_el0_impdef(char *p)
>> +{
>> +	no_trap_el0_impdef = true;
>> +	return 0;
>> +}
>> +early_param("no_trap_el0_impdef", parse_no_trap_el0_impdef);
>> +
>>  static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused)
>>  {
>> -	sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP);
>> +	if (no_trap_el0_impdef)
>> +		sysreg_clear_set(sctlr_el1, SCTLR_EL1_TIDCP, 0);
>> +	else
>> +		sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP);
> An id override for TIDCP1 seems simpler rather than an early param, and consistent to how we disable other 
> certain features through boot option like arm64.nosve or arm64.nompam. I see Catalin also suggested in that
> way in [1],any reason we cannot do it in that way?

Thanks for reminding me of that.

But the problem is on warm reset, SCTLR_ELx.tidcp resets to an unknown value.
This means using id_aa64mmfr1.tidcp1=0 override for TIDCP1 only skips setting
SCTLR_ELx.TIDCP to 1, it still can not guarantee the SCTLR_Ex.TIDCP is cleared.

BR,
Liao, Chang

> 
> [1] https://lore.kernel.org/all/aHqamaqueuk18NyS@arm.com/
> > Thanks.
>>  }
>>  
>>  static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused)