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Wed, 28 Oct 2026 07:37:44 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c46bd4e784esm601408766b.19.2026.10.28.07.37.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Oct 2026 07:37:43 -0700 (PDT) Message-ID: Date: Wed, 28 Oct 2026 15:37:40 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/4] phy: qcom: qmp-pcie: Add qref and refgen regulator vote for QCS8300 and SA8775p PHY To: Ziyue Zhang , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: Dmitry Baryshkov , peter.chen@oss.qualcomm.com, qiang.yu@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260916102023.2054761-1-ziyue.zhang@oss.qualcomm.com> <20260916102023.2054761-3-ziyue.zhang@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260916102023.2054761-3-ziyue.zhang@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: rIF7yjE61UyfsiNN2D0BgDZdC4rXodgN X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI4MDA1OCBTYWx0ZWRfX2fpY8ATX/Wlu Uqjg1FAM7vgyi8V57R1HoOQTmwwebN6Ejp1XtgPMWX3GSWdPz74LabrlrWAuFa5Mv3OQct81xtU Pumv83yJdZkndeuoWHfPndnkZNf8P8E= X-Authority-Analysis: v=2.4 cv=V+joQuni c=1 sm=1 tr=0 ts=6ae208ba cx=c_pps a=1Os3MKEOqt8YzSjcPV0cFA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=t5PPnQQkLeIUCWTc9swA:9 a=QEXdDO2ut3YA:10 a=hhpmQAJR8DioWGSBphRh:22 X-Proofpoint-ORIG-GUID: rIF7yjE61UyfsiNN2D0BgDZdC4rXodgN X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI4MDA1OCBTYWx0ZWRfX/TbeDtmXd3U/ c+lZ1WsUa4IyxWSYdD2ByeuHFC5XlajIomPBMGFoUXnIoRkTmlhfWRaVP1vuzIJUDwz0vYe0E+0 sAZtGuQPrFzIP7MKgvf3gstC8uRSymDnUYIa4BrDYT3r0XKPEKL2WdATLU5KbtexICRn+WgCV3O Q/NkJxfyFvSxrGxks442ZramsjDFQ4cyWB5CACpjcviqyGwYuyoVN9c0ctboKVZLs2FFN+yXCgA tFQ0DW2lEo5m6nidUuzTwQ08rT/viiAwA0/3lof+dtoiOaGes8UyVNP9PXUSHlOCD268SuIvg3q eV0jLUsyK32dTyISSeHqWdyotQ7/PnK/4EIHLgo07+X4tLG2kESi/LYyDSR41tEXhMbzzn2DjO2 5WhFQW0zGS3WmujJz9eKcq25D905gyZ5u6371KHx1L8rjoOS4qCHACcMLVe/DG2EmLE9WKjOBT+ NdLJkajmnbDT+ladiaw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-28_04,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 clxscore=1015 bulkscore=0 phishscore=0 impostorscore=0 priorityscore=1501 spamscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610280058 On 9/16/26 12:20 PM, Ziyue Zhang wrote: > Add a new sa8775p_qmp_phy_vreg_l that includes vdda-phy, vdda-pll, > vdda-qref, vdda-refgen and refgen supplies, and use it for QCS8300 > and SA8775p PCIe PHY configurations. This avoids modifying > sm8550_qmp_phy_vreg_l and breaking SM8550 and SM8650. > > These supplies were missing from the original driver, which was found > to be the root cause of occasional system crashes observed on QCS8300 > and SA8775p platforms. Without voting for these supplies, the PCIe PHY > lacks stable reference clock and voltage, so the PHY never becomes > ready and initialization times out: > > [ 7.303119] qcom-qmp-pcie-phy 1c04000.phy: phy initialization timed-out > [ 7.309948] phy phy-1c04000.phy.0: phy poweron failed --> -110 > > Note that due to a hardware issue, QREF actually depends on refgen3 > rather than refgen2 as documented; refgen3 is therefore voted manually > via the refgen supply as a workaround. > > Fixes: a05b6d5135ec ("phy: qcom-qmp-pcie: add support for sa8775p") > Fixes: ebf198f17b5a ("phy: qcom-qmp-pcie: add dual lane PHY support for QCS8300") > Signed-off-by: Ziyue Zhang > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 16 ++++++++++------ > 1 file changed, 10 insertions(+), 6 deletions(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > index da83358c97ea..ab81c6e584a8 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > @@ -4094,6 +4094,10 @@ static const char * const sm8550_qmp_phy_vreg_l[] = { > "vdda-phy", "vdda-pll", "vdda-qref", > }; > > +static const char * const sa8775p_qmp_phy_vreg_l[] = { > + "vdda-phy", "vdda-pll", "vdda-qref", "vdda-refgen", "refgen", > +}; I think we could grab them unconditionally, as QREF/REFGEN appears on most/all SoCs (perhaps with regulator_optional_get so that we defer the correctness of this to dt-bindings for any specific platform) Konrad