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([2001:b07:6468:f312:9520:22e6:6416:5c36]) by smtp.gmail.com with ESMTPSA id r18sm1705421wme.48.2019.09.26.04.12.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 Sep 2019 04:12:26 -0700 (PDT) Subject: Re: [PATCH 2/2] KVM: x86: Expose CLZERO and XSAVEERPTR to the guest To: Sebastian Andrzej Siewior , kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , x86@kernel.org References: <20190925213721.21245-1-bigeasy@linutronix.de> <20190925213721.21245-3-bigeasy@linutronix.de> From: Paolo Bonzini Message-ID: Date: Thu, 26 Sep 2019 13:12:25 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190925213721.21245-3-bigeasy@linutronix.de> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 25/09/19 23:37, Sebastian Andrzej Siewior wrote: > I was surprised to see that the guest reported `fxsave_leak' while the > host did not. After digging deeper I noticed that the bits are simply > masked out during enumeration. > The XSAVEERPTR feature is actually a bug fix on AMD which means the > kernel can disable a workaround. > While here, I've seen that CLZERO is also masked out. This opcode is > unprivilged so exposing it to the guest should not make any difference. > > Pass CLZERO and XSAVEERPTR to the guest if available on the host. > > Signed-off-by: Sebastian Andrzej Siewior > --- > arch/x86/kvm/cpuid.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index 22c2720cd948e..0ae9194d0f4d2 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -473,6 +473,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_entry2 *entry, u32 function, > > /* cpuid 0x80000008.ebx */ > const u32 kvm_cpuid_8000_0008_ebx_x86_features = > + F(CLZERO) | F(XSAVEERPTR) | > F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | > F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON); > > Applied (on top of Jim's CLZERO patch, so removing the CLZERO reference in the commit message). Paolo