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[88.112.131.206]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-537a8648b4esm753786e87.221.2024.09.26.03.28.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 Sep 2024 03:28:39 -0700 (PDT) Message-ID: Date: Thu, 26 Sep 2024 13:28:37 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/1] i2c: qcom-geni: Support systems with 32MHz serial engine clock Content-Language: en-US To: Manikanta Mylavarapu , andi.shyti@kernel.org, linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Cc: quic_srichara@quicinc.com, quic_varada@quicinc.com References: <20240926034304.3565278-1-quic_mmanikan@quicinc.com> From: Vladimir Zapolskiy In-Reply-To: <20240926034304.3565278-1-quic_mmanikan@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hello Manikanta. On 9/26/24 06:43, Manikanta Mylavarapu wrote: > In existing socs, I2C serial engine is sourced from XO (19.2MHz). > Where as in IPQ5424, I2C serial engine is sourced from GPLL0 (32MHz). > > The existing map table is based on 19.2MHz. This patch incorporate > the clock map table to derive the SCL clock from the 32MHz source > clock frequency. > > Signed-off-by: Manikanta Mylavarapu > --- > Changes in v2: > - Dropped IPQ5424 from the commit title > - Added else part to assign geni_i2c_clk_map_19p2mhz to itr > - Dropped MHZ macro and used HZ_PER_MHZ macro > - Expanded SE to serial engine > - Added the reason for 32MHz clock in commit message > > drivers/i2c/busses/i2c-qcom-geni.c | 19 ++++++++++++++++--- > 1 file changed, 16 insertions(+), 3 deletions(-) > > diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c > index 212336f724a6..22f2a0d83641 100644 > --- a/drivers/i2c/busses/i2c-qcom-geni.c > +++ b/drivers/i2c/busses/i2c-qcom-geni.c > @@ -16,6 +16,7 @@ > #include > #include > #include > +#include > > #define SE_I2C_TX_TRANS_LEN 0x26c > #define SE_I2C_RX_TRANS_LEN 0x270 > @@ -146,18 +147,30 @@ struct geni_i2c_clk_fld { > * clk_freq_out = t / t_cycle > * source_clock = 19.2 MHz > */ > -static const struct geni_i2c_clk_fld geni_i2c_clk_map[] = { > +static const struct geni_i2c_clk_fld geni_i2c_clk_map_19p2mhz[] = { > {KHZ(100), 7, 10, 11, 26}, > {KHZ(400), 2, 5, 12, 24}, > {KHZ(1000), 1, 3, 9, 18}, > }; > > +/* source_clock = 32 MHz */ > +static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = { > + {KHZ(100), 7, 14, 18, 40}, > + {KHZ(400), 4, 3, 11, 20}, > + {KHZ(1000), 4, 3, 6, 15}, > +}; Please double check the values. This is what I get: * for 100KHz: 32000000 / (40 * 7) ~ 114286, apparently 32000000 / (40 * 8) would be a better fit, however it's unclear what would be proper t_high / t_low values, * for 400KHz: it seems good, * for 1000KHz: 32000000 / (15 * 4) ~ 533333, which is almost 1/2 of the wanted bus frequency, so this one looks very wrong. Do you have any ideas how to get better bus frequency settings? > + > static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) > { > int i; > - const struct geni_i2c_clk_fld *itr = geni_i2c_clk_map; > + const struct geni_i2c_clk_fld *itr; > + > + if (clk_get_rate(gi2c->se.clk) == 32 * HZ_PER_MHZ) > + itr = geni_i2c_clk_map_32mhz; > + else > + itr = geni_i2c_clk_map_19p2mhz; > > - for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map); i++, itr++) { > + for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map_19p2mhz); i++, itr++) { Struct/data organization here is so weak, that here it's implicitly assumed that sizes of two arrays are equal. It could be kept as is of course, just pointing to it. > if (itr->clk_freq_out == gi2c->clk_freq_out) { > gi2c->clk_fld = itr; > return 0; -- Best wishes, Vladimir