From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from ixit.cz (ip-94-112-25-9.bb.vodafone.cz [94.112.25.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DF3031A046; Fri, 5 Dec 2025 12:11:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=94.112.25.9 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764936704; cv=none; b=pTFzD3ocU/Wmmz43mqWfLWSmM3FL3aMP7PBvjblZVRQGLcNl+GPKNM/WqozoY0XoXjKOwz1MmwcRtysV/OdBTvCOKavRuQ/LX23ufzf4L0jFCsFFCDt56JJcXywzgXChUcIib0BH7IQjdhyWnu3HEs3fDJrETCz0JOTaBuCwgUU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764936704; c=relaxed/simple; bh=48k4AgX+q3IBIkf0IGLJcXM2KiZiFNbkddmehWxWCIo=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=KdtmHM+iJ0uquDKnovSlWir+p3/D75r4yl/JFo5djInt5BRhhswoRK28ZDWpEOjSI8WR/TZdxk4lVbkjh8xbt4fCD2Op22QXeTO0IjxQK6Mbghr//TIQdekBWLBIfMtLlVMYI8kX5CXszowsQQCfq3wD4riFB9atXT4Cb/zUul4= ARC-Authentication-Results:i=1; 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bh=9K3BaIAz1YO5eT1F/Xdh0sXF5lL51JkibNNOPjMJcng=; b=ZbgpSJWpOBwS4UeAc0/p6zmcwnX+1JzC94XEZoFKNFCfqR19SzV+PWWHzZi0D0+KTEmRG3 9ffTmXDX73KnoswkhtzNK3a7liIqCMhgPA202Y3tWFBiXL46Ey4ylMGUuzle4nui977W/j 0vEpEI3qGjX4naySG+Y6MWZCvip8eDs= Message-ID: Date: Fri, 5 Dec 2025 13:11:37 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH WIP v2 5/8] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 CPHY init To: Konrad Dybcio , Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" Cc: Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org References: <20251204-qcom-cphy-v2-0-6b35ef8b071e@ixit.cz> <20251204-qcom-cphy-v2-5-6b35ef8b071e@ixit.cz> <03c137aa-bd31-43d7-aea8-489ec0102ab3@ixit.cz> Content-Language: en-US From: David Heidelberg Autocrypt: addr=david@ixit.cz; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 05/12/2025 13:00, Konrad Dybcio wrote: > On 12/5/25 12:56 PM, David Heidelberg wrote: >> On 05/12/2025 10:54, Konrad Dybcio wrote: >>> On 12/4/25 5:32 PM, David Heidelberg via B4 Relay wrote: >>>> From: Casey Connolly >>>> >>>> Add a PHY configuration sequence for the sdm845 which uses a Qualcomm >>>> Gen 2 version 1.1 CSI-2 PHY. >>>> >>>> The PHY can be configured as two phase or three phase in C-PHY or D-PHY >>>> mode. This configuration supports three-phase C-PHY mode. >>>> >>>> Signed-off-by: Casey Connolly >>>> Reviewed-by: Vladimir Zapolskiy >>>> Reviewed-by: Bryan O'Donoghue >>>> Co-developed-by: David Heidelberg >>>> Signed-off-by: David Heidelberg >>>> --- >>>>   .../platform/qcom/camss/camss-csiphy-3ph-1-0.c     | 74 +++++++++++++++++++++- >>>>   1 file changed, 72 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c >>>> index 3d30cdce33f96..7121aa97a19c4 100644 >>>> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c >>>> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c >>>> @@ -145,6 +145,7 @@ csiphy_lane_regs lane_regs_sa8775p[] = { >>>>   }; >>>>     /* GEN2 1.0 2PH */ >>>> +/* 5 entries: clock + 4 lanes */ >>>>   static const struct >>>>   csiphy_lane_regs lane_regs_sdm845[] = { >>>>       {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, >>>> @@ -219,6 +220,69 @@ csiphy_lane_regs lane_regs_sdm845[] = { >>>>       {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, >>>>   }; >>>>   +/* GEN2 1.0 3PH */ >>>> +/* 3 entries: 3 lanes (C-PHY) */ >>>> +static const struct >>>> +csiphy_lane_regs lane_regs_sdm845_3ph[] = { >>> >>> Here's a downstream snippet which seems to have more up-to-date settings >>> (checked against a doc and it seems to have changes made at the time of >>> the last edit of the doc) >>> >>> You'll notice it's split into 3 arrays of register sets - that's because >>> it applies setting for each lane.. something to keep in mind we could >>> optimize upstream data storage for (they are identical per lane in this >>> instance) one day >> >> see 87c2c2716523 ("media: qcom: camss: csiphy-3ph: Remove redundant PHY init sequence control loop") >> >> for the reason to flatten the regs array (thou outside the scope of this patchset). >> >> Regarding to the different value, I can test them, can you point to docs regarding why these regs has been changed and what the values means? >> >> I thought it's some default seq, but as you show there is multiple versions, it make sense to properly document what these regs do. > > I'll make that point to the relevant folks when they get around to refreshing > this driver, I'm not sure I can just tell you what all the magic sequences do.. > > The high-level description for all post-release PHY sequence updates is pretty > much always improves robustness as a result of "more better" electrical tuning. > It's also the case this time around. Since the original version works, but maybe it could work better (I'll do testing), I would do "upgrade" commit, so at least we know tho regs setups which works and someone can try deduct or document it in the future. If you try to poke the right people, that would be awesome. Thank you for noticing the new regs! :) David > > Konrad -- David Heidelberg