From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D83EF216394 for ; Fri, 10 Jan 2025 20:43:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736541820; cv=none; b=JNiQV97vGSWshJGSi1j32lqna0JJ08E9kJ4fBBSgiANpqwuGF8VeZTIZUNnodJHRmUb6zqVqhhi6qQYRROerKNv4Rzo/i/yx89TOY1lThiGZ6PE86jU6aUIY4DZYTrlXQCzLi6KImjyCjYniQdQl0PUbvhBN5OyU5AWLJUGOBiE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736541820; c=relaxed/simple; bh=wYnRlQkSS1vQL7tZraxnLcsI9Db6qd07NH5H+CpfGKU=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=EwjrXC8lJSpNicL2Nr3CqJQm5UzStUIwsEsyw7aYpgABr/bGtqWfS5rvaGFW6DSW/8lNGddS9akIU5M7qSoYHK6bWvfE3eWHhcXtnMZOjQWI+yascVkWSxmCWUJN1Hj4y3O2gt649RNwIvd12SttzByF3MPKozmdFb+NKC4AH4A= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tWLqk-000000006ot-2Iiv; Fri, 10 Jan 2025 15:43:22 -0500 Message-ID: Subject: Re: [PATCH 11/12] x86/mm: enable AMD translation cache extensions From: Rik van Riel To: Borislav Petkov Cc: Tom Lendacky , x86@kernel.org, linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, akpm@linux-foundation.org, nadav.amit@gmail.com, zhengqi.arch@bytedance.com, linux-mm@kvack.org Date: Fri, 10 Jan 2025 15:43:22 -0500 In-Reply-To: <20250110195838.GFZ4F77mf1kgyya5Du@fat_crate.local> References: <20241230175550.4046587-1-riel@surriel.com> <20241230175550.4046587-12-riel@surriel.com> <2cf92ecf-cd14-734a-6dd9-bd489321651e@amd.com> <8a8765c3d4f6154d38e00219cae739245d15cc1e.camel@surriel.com> <20250110195838.GFZ4F77mf1kgyya5Du@fat_crate.local> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.1 (3.54.1-1.fc41) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sender: riel@surriel.com On Fri, 2025-01-10 at 20:58 +0100, Borislav Petkov wrote: > On Fri, Jan 10, 2025 at 02:45:27PM -0500, Rik van Riel wrote: > > Is this the right location for that code, or > > do I need to move it somewhere else to > > guarantee TCE gets enabled on every CPU? >=20 > Didn't I answer this already? >=20 > https://lore.kernel.org/r/20250102115237.GGZ3Z-BUqBauHEfB10@fat_crate.loc= al >=20 > And you should put it in init_amd() as it runs on every CPU. >=20 Thank you for telling me about init_amd(). I wasn't sure where in amd.c to put it. --=20 All Rights Reversed.