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Thu, 06 Nov 2025 06:38:06 -0800 (PST) Received: from [192.168.88.32] ([212.105.155.83]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4776363da40sm48483375e9.2.2025.11.06.06.38.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Nov 2025 06:38:06 -0800 (PST) Message-ID: Date: Thu, 6 Nov 2025 15:38:04 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next v7 12/12] net: dsa: add driver for MaxLinear GSW1xx switch family To: "Sverdlin, Alexander" , "daniel@makrotopia.org" , "devicetree@vger.kernel.org" , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" Cc: "andrew@lunn.ch" , "olteanv@gmail.com" , "robh@kernel.org" , "lxu@maxlinear.com" , "john@phrozen.org" , "davem@davemloft.net" , "yweng@maxlinear.com" , "bxu@maxlinear.com" , "edumazet@google.com" , "conor+dt@kernel.org" , "fchan@maxlinear.com" , "ajayaraman@maxlinear.com" , "krzk+dt@kernel.org" , "hauke@hauke-m.de" , "horms@kernel.org" , "kuba@kernel.org" , "jpovazanec@maxlinear.com" , "linux@armlinux.org.uk" References: <8f36e6218221bb9dad6aabe4989ee4fc279581ce.camel@siemens.com> Content-Language: en-US From: Paolo Abeni In-Reply-To: <8f36e6218221bb9dad6aabe4989ee4fc279581ce.camel@siemens.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 11/4/25 9:03 AM, Sverdlin, Alexander wrote: > On Mon, 2025-11-03 at 12:20 +0000, Daniel Golle wrote: >> Add driver for the MaxLinear GSW1xx family of Ethernet switch ICs which >> are based on the same IP as the Lantiq/Intel GSWIP found in the Lantiq VR9 >> and Intel GRX MIPS router SoCs. The main difference is that instead of >> using memory-mapped I/O to communicate with the host CPU these ICs are >> connected via MDIO (or SPI, which isn't supported by this driver). >> Implement the regmap API to access the switch registers over MDIO to allow >> reusing lantiq_gswip_common for all core functionality. >> >> The GSW1xx also comes with a SerDes port capable of 1000Base-X, SGMII and >> 2500Base-X, which can either be used to connect an external PHY or SFP >> cage, or as the CPU port. Support for the SerDes interface is implemented >> in this driver using the phylink_pcs interface. >> >> Signed-off-by: Daniel Golle > > thank you for the patch! > > Finally I was able to run selftest/drivers/net/dsa/local_termination.sh > with only 2 unexpected failures on a GSW145 hardware (with TI AM62 > host CPU and its CPSW (not in switchdev mode) as CPU interface). > > The problems I had in the past were neither related to the GSW145 code, > nor to am65-cpsw-nuss, but to the test itself: > https://lore.kernel.org/all/20251104061723.483301-1-alexander.sverdlin@siemens.com/ > > The remaining failing test cases are: > TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address [FAIL] > reception succeeded, but should have failed > TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address, allmulti [FAIL] > reception succeeded, but should have failed > > So far I didn't notice any problems with untagged read-word IP traffic over > GSW145 ports. > > Do you have a suggestion what could I check further regarding the failing > test cases? As I understood, all of them pass on your side? Could be that due to different revisions of the relevant H/W? I tend to think we are better off merging the series as-is, and handle the above with follow-up, as needed. Any different opinions? Thanks, Paolo