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Wed, 17 Dec 2025 15:24:45 -0800 From: Nicolin Chen To: CC: , , , , , , , , , , , Subject: [PATCH v8 1/7] iommu/arm-smmu-v3: Explicitly set smmu_domain->stage for SVA Date: Wed, 17 Dec 2025 15:24:26 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E61:EE_|SN7PR12MB8769:EE_ X-MS-Office365-Filtering-Correlation-Id: 4eec842f-5c71-4938-837a-08de3dc37f5d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?hj9/yq9TY7haNB6EiAO3PY1gDq3LB+qxoT+GK4cmmzqS3gM0dffg9G/NjMYP?= =?us-ascii?Q?grmS3ha3ytshccTf3rbG1E/Aj5xrYKR5uuUqVJeIdcuotXyeObkVO0yoAPmI?= =?us-ascii?Q?nGIMO5xitfKa7GJFjoyghj3DUezbqxwO2U9fHYOU6Go0h+E93lmKPFTTC0wU?= =?us-ascii?Q?SHMQcCX8u+Wp6IyAWyWMRM1KxlLSQfFdFWalf0KMMZanZKVLbzwfL/vCraDg?= =?us-ascii?Q?qLn8EQH6K/9DoT737SySfuxwk+KPTQQp1JwNl8RkuuIEWbJqongS/nowK7s0?= =?us-ascii?Q?SDKsZU1n+xs/fb7MUu0OZafRrOXQXSBzcVFU6wyeoIjxMfK2h3Wj/PiPAmKR?= =?us-ascii?Q?aB8yqAjmarVChSsbVgHlRJynkGMo5MSBoqDKZVDMxhlRxuODz79cAkyve0qW?= =?us-ascii?Q?afC4Pd1j+WH46NpnLsK/DQetzcfOHeSOvVVlLB8uN2pQCBSfEH2WS1RQaqeg?= =?us-ascii?Q?E6QRgb3PuaMWzjt4i0qcTcru8FmKEf+deeqUz4SkzlKAZWJ4NPw0RX1AbnB8?= =?us-ascii?Q?ptFvpAaYgRwlXEsUy2F/eFc/xCrWVxSrdKz/YvrKMuvIGeFZp77qxxT/SXzI?= =?us-ascii?Q?PIJBy831z38UmkI3oExiqCHjzdHD+bQTEcUPiFIAYSBVINOaNXSmUycP+VwB?= =?us-ascii?Q?SW2DhxpvdKI/bOwFP4bn4691xJmSygXYwZyBvLs8kaOvbl+D23mM/6zHLP3H?= =?us-ascii?Q?kdOkO+AVYuBkO5Gzs5vqZBXMJRlgVfEu1xBiM+s3LJGpJ7g6j5e6qh813g9R?= =?us-ascii?Q?YzWQKfRsuno/zl9HBrAzllxEzoktxc2Lny/n7aIs8cAg5Bz6ySge336f3O5c?= =?us-ascii?Q?YZmhFTAn5p/ZnJYhOx9GYqoKzaQ0tHstg+ouW2U73Or+DkwZW7V0dBzJB2i9?= =?us-ascii?Q?wPrQfJolARX2WKzvycUzk098ajVeJBBYXMoG9sg77lTaMPcCbuOlYEgE4g1F?= =?us-ascii?Q?iffel97kps20SHlpizYM7QXovjGwW0Cm4r9A5HMI1lgV+bDq8wWGGWUFCwR9?= =?us-ascii?Q?RhzPKixGsqtgIKC8iegrsoNtGp3La0bGiH5OdqVtAbMpe/3xaopUuUUFjkcL?= =?us-ascii?Q?Q0HCZBWZ3xzcX+CgTIujkT1iGrQoJlUyhLM5cpvP4TNbl+j8L4NKJPF7oi/T?= =?us-ascii?Q?J4dz6aAZVUQWVUGj0rptEfS11V0pFDgXA3K+fTKol/md1fqroLXKGP9+CrEp?= =?us-ascii?Q?j//jF9sBbdG/1wjS5Sl3sn5S+5WZe0Vj73GEuEzt+H6Jtd/CjbZinVmF9Lft?= =?us-ascii?Q?zX7KMcN3GPOVuTG+sdqHr3+1lBsH8/Nurof7G0NI1wG6xKiDa7aF6wAtr96/?= =?us-ascii?Q?31UiMvYpbDClGtEMp8ZRfVYeweLYCUP1OEgeUDjsxQhOKdyqZqfbl0cvwDqh?= =?us-ascii?Q?cW+17AJjOWAptbgvV/QDKtFGOcSDTqh2hfClhsy5sXnae9EtfSS2bGTKWLe0?= =?us-ascii?Q?TgvAuvKtpDUmAA/dreWP1PL3lALQCQvA2QngEuLRPK9l/PfYwEgFK4m4F/b+?= =?us-ascii?Q?ye0JSlAoCK7jNhyUmqWgHbnEV+IMlVSAYu8ksh4NKCbz5v321IEBpFxnJzvc?= =?us-ascii?Q?+eL3oVAKJX6FY1aVgz8=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Dec 2025 23:24:59.5991 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4eec842f-5c71-4938-837a-08de3dc37f5d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E61.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8769 Both the ARM_SMMU_DOMAIN_S1 case and the SVA case use ASID, requiring ASID based invalidation commands to flush the TLB. Define an ARM_SMMU_DOMAIN_SVA to make the SVA case clear to share the same path with the ARM_SMMU_DOMAIN_S1 case, which will be a part of the routine to build a new per-domain invalidation array. There is no function change. Suggested-by: Jason Gunthorpe Acked-by: Balbir Singh Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +++ 3 files changed, 5 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index ae23aacc3840..5c0b38595d20 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -858,6 +858,7 @@ struct arm_smmu_master { enum arm_smmu_domain_stage { ARM_SMMU_DOMAIN_S1 = 0, ARM_SMMU_DOMAIN_S2, + ARM_SMMU_DOMAIN_SVA, }; struct arm_smmu_domain { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 59a480974d80..6097f1f540d8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -346,6 +346,7 @@ struct iommu_domain *arm_smmu_sva_domain_alloc(struct device *dev, * ARM_SMMU_FEAT_RANGE_INV is present */ smmu_domain->domain.pgsize_bitmap = PAGE_SIZE; + smmu_domain->stage = ARM_SMMU_DOMAIN_SVA; smmu_domain->smmu = smmu; ret = xa_alloc(&arm_smmu_asid_xa, &asid, smmu_domain, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index d16d35c78c06..9d9f24a08062 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3065,6 +3065,9 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev, arm_smmu_install_ste_for_dev(master, &target); arm_smmu_clear_cd(master, IOMMU_NO_PASID); break; + default: + WARN_ON(true); + break; } arm_smmu_attach_commit(&state); -- 2.43.0