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Fri, 19 Dec 2025 12:12:08 -0800 From: Nicolin Chen To: CC: , , , , , , , , , , , Subject: [PATCH v9 1/7] iommu/arm-smmu-v3: Explicitly set smmu_domain->stage for SVA Date: Fri, 19 Dec 2025 12:11:23 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000026C4:EE_|BL1PR12MB5802:EE_ X-MS-Office365-Filtering-Correlation-Id: 3368674f-eeb9-4494-4142-08de3f3aeec5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Qfi3ue9R6Vu1hr9o4vGdzFeCimH9oANH5mXfr2vmlVGgXyGSQQZQYypudoBy?= =?us-ascii?Q?N5vD/BF7OKp5yZrCTn61I9u8yPOhJ7ffSop/g5iOYOnXwLmz53ufs0tjohq3?= =?us-ascii?Q?p2Z8Etr4dFjqYXbSjHg7NI8u0fYjNY0MUBqY+KXDeek8cGKbj8ipCKGp9hXl?= =?us-ascii?Q?TG0NrWRx4GIdCDo8foDJd1SzypmdRMlLAo9LSfiWiqvSBOI9+QeQicH0/3l2?= =?us-ascii?Q?P6HTZZTZL5opHGaJ064BiJ8tAlOcNyGdIZs2hQr0gGP24gF4BtCNsUYzPM/q?= =?us-ascii?Q?fDHFUoBppreDP2b6oYNuaAWGF5L26OvKQ2U5z7q0RsY/R9koTOGUksjHAq/w?= =?us-ascii?Q?ARp+hWkamB3g1fBxuYb7mAx/SLytoB7UptIuLC61Q6GBzugFLMgYnBLN7aGF?= =?us-ascii?Q?InYFCWN6Qbh3rVtufi4RJ5vn7t1qL5yAs3Y/F6gvl4eQAchjCEBTpYo9N90/?= =?us-ascii?Q?KVGOUMUc4PRz6dW7pYDaBXFGksZGLXH48RYfruscfPdYhHbAuso9nCq3Qbr+?= =?us-ascii?Q?wOz/2i8BPGLZulfhEyuIsCRqZmVt/zQn/CTgxV83TfOqozrB8oJDFOrtGLD4?= =?us-ascii?Q?n5FKMY9kfcOjkJlK85pcFDCmL+Ep/yfQh54vORKRA1VOhYC5NY60Ed7DXP89?= =?us-ascii?Q?pqkCJlwM/YjPpsM8YlhjCqsDHyL13GfRf7XCVgiL5F/uDhnCXXBWMP680pUF?= =?us-ascii?Q?c28CpA5mC6IDetnOKjYW5cI4SUCInITj/kt7C+IdV0RrJiFKUKu7cGvpkqm7?= =?us-ascii?Q?1XaCX/LzreL4SIebUEUrqQacqV7rnojoxcE1ubb/oGsSxieAVSJCyxwDF91e?= =?us-ascii?Q?dHhgqdIabSVommWWIZk5xlkeSJfI/kB8zvgnHUINOn8T5SJC/jd9sArXgJ/s?= =?us-ascii?Q?xZkn/g+s+SxaMjf8cTjaEjS+oE2VCorj3PxnVX9AeYytQEB/0H9AHVam6tpn?= =?us-ascii?Q?W0aUG457dQDhLAwzmzb7aH05Z4iO/SdpUxcgWrCix9E5vj9N5ZO8ibQXepIn?= =?us-ascii?Q?xF5VSDaW1r6g/LvcIV6nk+D1kE/eWDLUBTOML1qlQzB5yxeFc0zFfPPSOPUG?= =?us-ascii?Q?rHJVy4uv1kU1wpQGKbsHPENqULU/LzzLbQV4eif1XruL98m4xM5iBxtVirL/?= =?us-ascii?Q?PWuxxZ0dXsH/MBA+0y+YQqhQ/kq487+nwzJLczYu49hRfJgv5TgFItAitAXs?= =?us-ascii?Q?dNYQj5Eh4yTtNMIE/R6k+GxLlya/pRp1BctW0X8zKZYCdw45CzXuncvT0pvx?= =?us-ascii?Q?bgvRUSnu3pTst2L0voAKtIT4JGGkN/WQ3tKh90B9fDjxnugYSMS++BRPUpG+?= =?us-ascii?Q?HSt4Pd5qZ7DPxSLBrLrLahDsqLLzD9eEhr3hIyl/RVM1m3pZWWC+MYPBNpG+?= =?us-ascii?Q?GaSlcRcg18OPixszH6Bngdp+tq1fEYrJzUvKmbSFc1I9Ego0nfDTDJjkGdr7?= =?us-ascii?Q?YRG0UehBUJPvAXoqcksx+BCumOu9ZpUN+SFGAulvAW0e2BAPenYsSmSefVRf?= =?us-ascii?Q?EyM/q2HwKvh2z+1/wasAMIT52qQk1z3xVx5I1snhGzXpGPicweAJPwQtdxV9?= =?us-ascii?Q?VLvKThjgCo5nyhH48cc=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(7416014)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2025 20:12:27.8388 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3368674f-eeb9-4494-4142-08de3f3aeec5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000026C4.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5802 Both the ARM_SMMU_DOMAIN_S1 case and the SVA case use ASID, requiring ASID based invalidation commands to flush the TLB. Define an ARM_SMMU_DOMAIN_SVA to make the SVA case clear to share the same path with the ARM_SMMU_DOMAIN_S1 case, which will be a part of the routine to build a new per-domain invalidation array. There is no function change. Suggested-by: Jason Gunthorpe Acked-by: Balbir Singh Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +++ 3 files changed, 5 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index ae23aacc3840..5c0b38595d20 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -858,6 +858,7 @@ struct arm_smmu_master { enum arm_smmu_domain_stage { ARM_SMMU_DOMAIN_S1 = 0, ARM_SMMU_DOMAIN_S2, + ARM_SMMU_DOMAIN_SVA, }; struct arm_smmu_domain { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 59a480974d80..6097f1f540d8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -346,6 +346,7 @@ struct iommu_domain *arm_smmu_sva_domain_alloc(struct device *dev, * ARM_SMMU_FEAT_RANGE_INV is present */ smmu_domain->domain.pgsize_bitmap = PAGE_SIZE; + smmu_domain->stage = ARM_SMMU_DOMAIN_SVA; smmu_domain->smmu = smmu; ret = xa_alloc(&arm_smmu_asid_xa, &asid, smmu_domain, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index d16d35c78c06..9d9f24a08062 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3065,6 +3065,9 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev, arm_smmu_install_ste_for_dev(master, &target); arm_smmu_clear_cd(master, IOMMU_NO_PASID); break; + default: + WARN_ON(true); + break; } arm_smmu_attach_commit(&state); -- 2.43.0