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From: "CK Hu (胡俊光)" <ck.hu@mediatek.com>
To: "robh@kernel.org" <robh@kernel.org>,
	"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
	"Paul-pl Chen (陳柏霖)" <Paul-pl.Chen@mediatek.com>,
	"conor+dt@kernel.org" <conor+dt@kernel.org>,
	"AngeloGioacchino Del Regno"
	<angelogioacchino.delregno@collabora.com>,
	"chunkuang.hu@kernel.org" <chunkuang.hu@kernel.org>
Cc: "matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
	"treapking@chromium.org" <treapking@chromium.org>,
	"Singo Chang (張興國)" <Singo.Chang@mediatek.com>,
	Project_Global_Chrome_Upstream_Group
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"Jason-JH Lin (林睿祥)" <Jason-JH.Lin@mediatek.com>,
	"Nancy Lin (林欣螢)" <Nancy.Lin@mediatek.com>,
	"Xiandong Wang (王先冬)" <Xiandong.Wang@mediatek.com>,
	"linux-mediatek@lists.infradead.org"
	<linux-mediatek@lists.infradead.org>,
	"Sunny Shen (沈姍姍)" <Sunny.Shen@mediatek.com>,
	"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
	"Sirius Wang (王皓昱)" <Sirius.Wang@mediatek.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 08/12] drm/mediatek: add EXDMA support for MT8196
Date: Thu, 16 Jan 2025 01:45:33 +0000	[thread overview]
Message-ID: <df7472540cd546ed9ee0c2fb3e10c666b442a68e.camel@mediatek.com> (raw)
In-Reply-To: <20250110123835.2719824-10-paul-pl.chen@mediatek.com>

Hi, Paul:


 


On Fri, 2025-01-10 at 20:34 +0800,paul-pl.chen wrote:
> 
> > From: "Nancy.Lin" <nancy.lin@mediatek.com>
> 
> > 
> 
> > EXDMA is a DMA engine for reading data from DRAM with
> 
> > various DRAM footprints and data formats. For input
> 
> > sources in certain color formats and color domains,
> 
> > EXDMA also includes a color transfer function to
> 
> > process pixels into a consistent color domain.
> 
> > 
> 
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> 
> > Signed-off-by: Paul-pl.Chen <paul-pl.chen@mediatek.com>
> 
> > ---
> 
>  
> 
> [snip]
> 
>  
> 
> > +#define DISP_REG_OVL_L0_CLRFMT                      0x050
> 
> > +#define OVL_CON_FLD_CLRFMT                          GENMASK(3, 0)
> 
> > +#define OVL_CON_CLRFMT_MAN                          BIT(4)
> 
> > +#define OVL_CON_FLD_CLRFMT_NB                       GENMASK(9, 8)
> 
> > +#define OVL_CON_CLRFMT_NB_10_BIT                    BIT(8)
> 
> > +#define OVL_CON_BYTE_SWAP                           BIT(16)
> 
> > +#define OVL_CON_RGB_SWAP                            BIT(17)
> 
> > +#define OVL_CON_CLRFMT_RGB565                       0x000
> 
> > +#define OVL_CON_CLRFMT_BGR888                       0x001
> 
> > +#define OVL_CON_CLRFMT_BGRA8888                             0x002
> 
> > +#define OVL_CON_CLRFMT_ABGRB8888                    0x003
> 
> > +#define OVL_CON_CLRFMT_UYVY                         0x004
> 
> > +#define OVL_CON_CLRFMT_YUYV                         0x005
> 
> > +#define OVL_CON_CLRFMT_BGR565                       (0x000 | OVL_CON_BYTE_SWAP)
> 
> > +#define OVL_CON_CLRFMT_RGB888                       (0x001 | OVL_CON_BYTE_SWAP)
> 
> > +#define OVL_CON_CLRFMT_RGBA8888                             (0x002 | OVL_CON_BYTE_SWAP)
> 
> > +#define OVL_CON_CLRFMT_ARGB8888                             (0x003 | OVL_CON_BYTE_SWAP)
> 
> > +#define OVL_CON_CLRFMT_VYUY                         (0x004 | OVL_CON_BYTE_SWAP)
> 
> > +#define OVL_CON_CLRFMT_YVYU                         (0x005 | OVL_CON_BYTE_SWAP)
> 
> > +#define OVL_CON_CLRFMT_PBGRA8888                    (0x003 | OVL_CON_CLRFMT_MAN)
> 
> > +#define OVL_CON_CLRFMT_PARGB8888              (OVL_CON_CLRFMT_PBGRA8888 | \
> 
> > +                                                    OVL_CON_BYTE_SWAP)
> 
> > +#define OVL_CON_CLRFMT_PRGBA8888              (OVL_CON_CLRFMT_PBGRA8888 | \
> 
> > +                                                    OVL_CON_RGB_SWAP)
> 
> > +#define OVL_CON_CLRFMT_PABGR8888              (OVL_CON_CLRFMT_PBGRA8888 | \
> 
> > +                                                    OVL_CON_RGB_SWAP | \
> 
> > +                                                    OVL_CON_BYTE_SWAP)
> 
>  
> 
> The color format definition is identical with ovl driver. Try to merge them.
> 
>  
> 
> > +#define DISP_REG_OVL_RDMA0_CTRL                     0x100
> 
> > +#define DISP_RDMA0_EN                               BIT(0)
> 
> > +#define DISP_REG_OVL_RDMA_BURST_CON1        0x1f4
> 
> > +#define DISP_RDMA_BURST_CON1_BURST16_EN                     BIT(28)
> 
> > +#define DISP_RDMA_BURST_CON1_DDR_EN                 BIT(30)
> 
> > +#define DISP_RDMA_BURST_CON1_DDR_ACK_EN                     BIT(31)
> 
> > +#define DISP_REG_OVL_DUMMY_REG                      0x200
> 
> > +#define DISP_OVL_EXT_DDR_EN_OPT                             BIT(2)
> 
> > +#define DISP_OVL_FORCE_EXT_DDR_EN                   BIT(3)
> 
> > +#define DISP_REG_OVL_GDRDY_PRD                      0x208
> 
>  
> 
> [snip]
> 
>  
> 
> > +
> 
> > +static const u32 formats[] = {
> 
>  
> 
> This array is identical with mt8195_formats[], try to merge them.
> 
>  
> 
> > +      DRM_FORMAT_XRGB8888,
> 
> > +      DRM_FORMAT_ARGB8888,
> 
> > +      DRM_FORMAT_BGRX8888,
> 
> > +      DRM_FORMAT_BGRA8888,
> 
> > +      DRM_FORMAT_ABGR8888,
> 
> > +      DRM_FORMAT_XBGR8888,
> 
> > +      DRM_FORMAT_RGBX8888,
> 
> > +      DRM_FORMAT_RGBA8888,
> 
> > +      DRM_FORMAT_RGB888,
> 
> > +      DRM_FORMAT_BGR888,
> 
> > +      DRM_FORMAT_RGB565,
> 
> > +      DRM_FORMAT_UYVY,
> 
> > +      DRM_FORMAT_YUYV,
> 
> > +      DRM_FORMAT_XRGB2101010,
> 
> > +      DRM_FORMAT_ARGB2101010,
> 
> > +      DRM_FORMAT_RGBX1010102,
> 
> > +      DRM_FORMAT_RGBA1010102,
> 
> > +      DRM_FORMAT_XBGR2101010,
> 
> > +      DRM_FORMAT_ABGR2101010,
> 
> > +      DRM_FORMAT_BGRX1010102,
> 
> > +      DRM_FORMAT_BGRA1010102,
> 
> > +};
> 
> > +
> 
>  
> 
> [snip]
> 
>  
> 
> > +
> 
> > +static unsigned int mtk_disp_exdma_fmt_convert(unsigned int fmt, unsigned int blend_mode)
> 
>  
> 
> This function is almost the same as mtk_ovl_fmt_convert(), try to merge them.
> 
>  
> 
> Regards,
> 
> CK
> 
>  
> 
> > +{
> 
> > +      /*
> 
> > +       * DRM_FORMAT: bit 32->0, OVL_FMT: bit 0->32,
> 
> > +       * so DRM_FORMAT_RGB888 = OVL_CON_CLRFMT_BGR888
> 
> > +       */
> 
> > +      switch (fmt) {
> 
> > +      default:
> 
> > +      case DRM_FORMAT_BGR565:
> 
> > +              return OVL_CON_CLRFMT_RGB565;
> 
> > +      case DRM_FORMAT_RGB565:
> 
> > +              return OVL_CON_CLRFMT_BGR565;
> 
> > +      case DRM_FORMAT_RGB888:
> 
> > +              return OVL_CON_CLRFMT_BGR888;
> 
> > +      case DRM_FORMAT_BGR888:
> 
> > +              return OVL_CON_CLRFMT_RGB888;
> 
> > +      case DRM_FORMAT_RGBX8888:
> 
> > +      case DRM_FORMAT_RGBA8888:
> 
> > +      case DRM_FORMAT_RGBA1010102:
> 
> > +      case DRM_FORMAT_RGBX1010102:
> 
> > +              return ((blend_mode == DRM_MODE_BLEND_PREMULTI) ?
> 
> > +                      OVL_CON_CLRFMT_PABGR8888 : OVL_CON_CLRFMT_ABGRB8888) |
> 
> > +                      (is_10bit_rgb(fmt) ? OVL_CON_CLRFMT_NB_10_BIT : 0);
> 
> > +      case DRM_FORMAT_BGRX8888:
> 
> > +      case DRM_FORMAT_BGRA8888:
> 
> > +      case DRM_FORMAT_BGRA1010102:
> 
> > +      case DRM_FORMAT_BGRX1010102:
> 
> > +              return ((blend_mode == DRM_MODE_BLEND_PREMULTI) ?
> 
> > +                      OVL_CON_CLRFMT_PARGB8888 : OVL_CON_CLRFMT_ARGB8888) |
> 
> > +                      (is_10bit_rgb(fmt) ? OVL_CON_CLRFMT_NB_10_BIT : 0);
> 
> > +      case DRM_FORMAT_XRGB8888:
> 
> > +      case DRM_FORMAT_ARGB8888:
> 
> > +      case DRM_FORMAT_ARGB2101010:
> 
> > +      case DRM_FORMAT_XRGB2101010:
> 
> > +              return ((blend_mode == DRM_MODE_BLEND_PREMULTI) ?
> 
> > +                      OVL_CON_CLRFMT_PBGRA8888 : OVL_CON_CLRFMT_BGRA8888) |
> 
> > +                      (is_10bit_rgb(fmt) ? OVL_CON_CLRFMT_NB_10_BIT : 0);
> 
> > +      case DRM_FORMAT_XBGR8888:
> 
> > +      case DRM_FORMAT_ABGR8888:
> 
> > +      case DRM_FORMAT_ABGR2101010:
> 
> > +      case DRM_FORMAT_XBGR2101010:
> 
> > +              return ((blend_mode == DRM_MODE_BLEND_PREMULTI) ?
> 
> > +                      OVL_CON_CLRFMT_PRGBA8888 : OVL_CON_CLRFMT_RGBA8888) |
> 
> > +                      (is_10bit_rgb(fmt) ? OVL_CON_CLRFMT_NB_10_BIT : 0);
> 
> > +      case DRM_FORMAT_UYVY:
> 
> > +              return OVL_CON_CLRFMT_UYVY;
> 
> > +      case DRM_FORMAT_YUYV:
> 
> > +              return OVL_CON_CLRFMT_YUYV;
> 
> > +      }
> 
> > +}
> 
> > +
> 




 

  reply	other threads:[~2025-01-16  1:45 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-10 12:33 [PATCH 00/12] Add Mediatek Soc DRM support for mt8196 paul-pl.chen
2025-01-10 12:33 ` [PATCH 01/12] dt-bindings: arm: mediatek: mmsys: add compatible for MT8196 paul-pl.chen
2025-01-10 12:58   ` Krzysztof Kozlowski
2025-01-13 11:25     ` Fei Shao
2025-01-13 11:30       ` Krzysztof Kozlowski
2025-01-15  9:18     ` Paul-pl Chen (陳柏霖)
2025-01-10 12:33 ` [PATCH 02/12] dt-bindings: soc: mediatek: add mutex yaml " paul-pl.chen
2025-01-10 12:33 ` [PATCH 03/12] dt-bindings: display: mediatek: add EXDMA " paul-pl.chen
2025-01-10 13:01   ` Krzysztof Kozlowski
2025-01-17 10:36     ` Paul-pl Chen (陳柏霖)
2025-01-18  8:37       ` Krzysztof Kozlowski
2025-01-21 17:07         ` Paul-pl Chen (陳柏霖)
2025-02-11  8:23         ` Paul-pl Chen (陳柏霖)
2025-02-12  5:40           ` Krzysztof Kozlowski
2025-01-10 12:33 ` paul-pl.chen
2025-01-10 13:54   ` Rob Herring (Arm)
2025-01-14  5:49     ` Paul-pl Chen (陳柏霖)
2025-01-14 10:34       ` AngeloGioacchino Del Regno
2025-01-15 12:13         ` Paul-pl Chen (陳柏霖)
2025-01-18  9:22       ` Krzysztof Kozlowski
2025-01-21 17:14         ` Paul-pl Chen (陳柏霖)
2025-01-23  6:11         ` Paul-pl Chen (陳柏霖)
2025-01-23  6:25           ` Chen-Yu Tsai
2025-01-23 16:09             ` Paul-pl Chen (陳柏霖)
2025-01-23  7:21           ` Krzysztof Kozlowski
2025-01-23 16:14             ` Paul-pl Chen (陳柏霖)
2025-01-23 16:20               ` Chen-Yu Tsai
2025-01-10 12:34 ` [PATCH 04/12] dt-bindings: display: mediatek: add BLENDER " paul-pl.chen
2025-01-10 13:54   ` Rob Herring (Arm)
2025-01-10 12:34 ` [PATCH 05/12] dt-bindings: display: mediatek: add OUTPROC " paul-pl.chen
2025-01-10 13:54   ` Rob Herring (Arm)
2025-01-10 12:34 ` [PATCH 06/12] soc: mediatek: add mmsys support " paul-pl.chen
2025-01-10 12:34 ` [PATCH 07/12] soc: mediatek: mutex: add mutex " paul-pl.chen
2025-01-20  8:04   ` Chen-Yu Tsai
2025-01-10 12:34 ` [PATCH 08/12] drm/mediatek: add EXDMA " paul-pl.chen
2025-01-16  1:45   ` CK Hu (胡俊光) [this message]
2025-01-20  9:54   ` Chen-Yu Tsai
2025-01-10 12:34 ` [PATCH 09/12] drm/mediatek: add BLENDER " paul-pl.chen
2025-02-12  3:45   ` CK Hu (胡俊光)
2025-01-10 12:34 ` [PATCH 10/12] drm/mediatek: add OUTPROC " paul-pl.chen
2025-02-12  4:08   ` CK Hu (胡俊光)
2025-02-21 11:54     ` Paul-pl Chen (陳柏霖)
2025-01-10 12:34 ` [PATCH 11/12] drm/mediatek: add ovlsys_adaptor " paul-pl.chen
2025-02-12  7:09   ` CK Hu (胡俊光)
2025-02-21 12:34     ` Paul-pl Chen (陳柏霖)
2025-01-10 12:34 ` [PATCH 12/12] drm/mediatek: Add support for multiple mmsys in the one mediatek-drm driver paul-pl.chen
2025-02-12  9:30   ` CK Hu (胡俊光)
2025-02-21 12:39     ` Paul-pl Chen (陳柏霖)
2025-01-13 12:50 ` [PATCH 00/12] Add Mediatek Soc DRM support for mt8196 AngeloGioacchino Del Regno
2025-01-15  8:05   ` Paul-pl Chen (陳柏霖)

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