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([2a01:e0a:106d:1080:5788:c4e1:cf35:7211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-496c4615681sm77642695e9.11.2026.07.28.05.58.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Jul 2026 05:58:13 -0700 (PDT) Message-ID: Date: Tue, 28 Jul 2026 14:58:11 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: Neil Armstrong Subject: Re: [PATCH v16 3/3] of: Respect #{iommu,msi}-cells in maps To: Dmitry Baryshkov Cc: Vijayanand Jitta , Nipun Gupta , Nikhil Agarwal , Joerg Roedel , Will Deacon , Robin Murphy , Lorenzo Pieralisi , Marc Zyngier , Thomas Gleixner , Rob Herring , Saravana Kannan , Richard Zhu , Lucas Stach , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Juergen Gross , Stefano Stabellini , Oleksandr Tyshchenko , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, imx@lists.linux.dev, xen-devel@lists.xenproject.org, Charan Teja Kalla References: <20260603-parse_iommu_cells-v16-0-dc509dacb19a@oss.qualcomm.com> <20260603-parse_iommu_cells-v16-3-dc509dacb19a@oss.qualcomm.com> <3f5c974f-425d-47a5-9fda-e05de1f39d79@linaro.org> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 7/28/26 13:34, Dmitry Baryshkov wrote: > On Thu, Jul 23, 2026 at 03:17:24PM +0200, Neil Armstrong wrote: >> Hi, >> >> On 6/3/26 09:13, Vijayanand Jitta wrote: >>> From: Robin Murphy >>> >>> So far our parsing of {iommu,msi}-map properties has always blindly >>> assumed that the output specifiers will always have exactly 1 cell. >>> This typically does happen to be the case, but is not actually enforced >>> (and the PCI msi-map binding even explicitly states support for 0 or 1 >>> cells) - as a result we've now ended up with dodgy DTs out in the field >>> which depend on this behaviour to map a 1-cell specifier for a 2-cell >>> provider, despite that being bogus per the bindings themselves. >>> >>> Since there is some potential use in being able to map at least single >>> input IDs to multi-cell output specifiers (and properly support 0-cell >>> outputs as well), add support for properly parsing and using the target >>> nodes' #cells values, albeit with the unfortunate complication of still >>> having to work around expectations of the old behaviour too. >>> >>> Since there are multi-cell output specifiers, the callers of of_map_id() >>> may need to get the exact cell output value for further processing. >>> Update of_map_id() to set args_count in the output to reflect the actual >>> number of output specifier cells. >>> >>> Signed-off-by: Robin Murphy >>> Signed-off-by: Charan Teja Kalla >>> Signed-off-by: Vijayanand Jitta >>> --- >>> drivers/of/base.c | 168 +++++++++++++++++++++++++++++++++++++++++------------ >>> include/linux/of.h | 6 +- >>> 2 files changed, 135 insertions(+), 39 deletions(-) >>> >>> diff --git a/drivers/of/base.c b/drivers/of/base.c >>> index d658c2620135..ac7961cbab94 100644 >>> --- a/drivers/of/base.c >>> +++ b/drivers/of/base.c >>> @@ -2116,19 +2116,49 @@ int of_find_last_cache_level(unsigned int cpu) >>> return cache_level; >>> } >>> +/* >>> + * Some DTs have an iommu-map targeting a 2-cell IOMMU node while >>> + * specifying only 1 cell. Fortunately they all consist of value '1' >>> + * as the 2nd cell entry with the same target, so check for that pattern. >>> + * >>> + * Example: >>> + * IOMMU node: >>> + * #iommu-cells = <2>; >>> + * >>> + * Device node: >>> + * iommu-map = <0x0000 &smmu 0x0000 0x1>, >>> + * <0x0100 &smmu 0x0100 0x1>; >> >> So the sm8650 PCIe controllers has: >> >> pcie@1c08000: >> iommu-map = <0 &apps_smmu 0x1480 0x1>, >> <0x100 &apps_smmu 0x1481 0x1>; > > To silence the warning, update the iommu maps to: > > iommu-map = <0 &apps_smmu 0x1480 0x0 0x1>, > <0x100 &apps_smmu 0x1481 0x0 0x1>; > > Will do, I was surprised none of the DT were fixed. Thanks, Neil