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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29f271bc8a0sm429515ad.92.2025.12.11.17.12.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Dec 2025 17:12:29 -0800 (PST) Message-ID: Date: Fri, 12 Dec 2025 09:12:19 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 5/8] dt-bindings: arm: add an interrupt property for Coresight CTCU To: Rob Herring Cc: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Mao Jinlong , Bjorn Andersson , Konrad Dybcio , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski References: <20251211-enable-byte-cntr-for-ctcu-v8-0-3e12ff313191@oss.qualcomm.com> <20251211-enable-byte-cntr-for-ctcu-v8-5-3e12ff313191@oss.qualcomm.com> <20251211133723.GA859302-robh@kernel.org> Content-Language: en-US From: Jie Gan In-Reply-To: <20251211133723.GA859302-robh@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=LZ0xKzfi c=1 sm=1 tr=0 ts=693b6bff cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=SkUS4XPTP4F0jhogtscA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: naZ20uYH5ZA-9JgPOJ7FgpuOJ5ihMn9k X-Proofpoint-ORIG-GUID: naZ20uYH5ZA-9JgPOJ7FgpuOJ5ihMn9k X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjEyMDAwOCBTYWx0ZWRfX9OfdJWvz+krI ENXCXME8Gpgpsa1e6oluBLCg9WRcfoZtOlBl6UHjp7RbclRLgBe+16YSQqop2GJ81mauzgCq7CP 7W2W2HNY4LTzho4Il1c2K0K7QzwdmEZyfMbCjqYA+Kio+1o13s51oQPUIrProxFHYBu3Ap3Aj3X 6MVDxX2d1Bn5l6pG0KSKXIQlUogVmlkKzBtWJQodcTukVKl8FVFpfz9ZH0ujwbkvSnmEDEC4PPQ 3YgZ7O7ZHQEXfbHvKxpWVl7RHbfSjbE6/uPU/d8JGxvmQYgnj1t8zWarx5ewoHQ6P8QpxjrG1u4 +5Ndpc/XkeJuJw7i8y7JreoT54CCFA13Vq2qPmvyI7UZAJcHVQLHIMpbDbDfmKvqS5sBatEJDsA v2Ian21zPvHiEMPoEBjkD3n9mfonNg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-12_01,2025-12-11_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 suspectscore=0 impostorscore=0 clxscore=1015 phishscore=0 priorityscore=1501 spamscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512120008 On 12/11/2025 9:37 PM, Rob Herring wrote: > On Thu, Dec 11, 2025 at 02:10:44PM +0800, Jie Gan wrote: >> Add an interrupt property to CTCU device. The interrupt will be triggered >> when the data size in the ETR buffer exceeds the threshold of the >> BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register >> of CTCU device will enable the interrupt. >> >> Acked-by: Krzysztof Kozlowski >> Reviewed-by: Mike Leach >> Signed-off-by: Jie Gan >> --- >> .../devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 17 +++++++++++++++++ >> 1 file changed, 17 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml >> index c969c16c21ef..90f88cc6cd3e 100644 >> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml >> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml >> @@ -39,6 +39,16 @@ properties: >> items: >> - const: apb >> >> + interrupts: >> + items: >> + - description: Byte cntr interrupt for the first etr device >> + - description: Byte cntr interrupt for the second etr device >> + >> + interrupt-names: >> + items: >> + - const: etrirq0 >> + - const: etrirq1 > > Names are kind of pointless when it is just foo. Hi Rob, I was naming them as etr0/etr1. Are these names acceptable? The interrupts are assigned exclusively to a specific ETR device. But Suzuki is concerned that this might cause confusion because the ETR device is named randomly in the driver. Suzuki suggested using ‘port-0’ and ‘port-1’ and would also like to hear your feedback on these names. Usually, the probe sequence follows the order of the addresses. In our specification, ‘ETR0’ is always probed before ‘ETR1’ because its address is lower. I would greatly appreciate your suggestion for the interrupt name, if possible. Thanks, Jie > >> + >> label: >> description: >> Description of a coresight device. >> @@ -60,6 +70,8 @@ additionalProperties: false >> >> examples: >> - | >> + #include >> + >> ctcu@1001000 { >> compatible = "qcom,sa8775p-ctcu"; >> reg = <0x1001000 0x1000>; >> @@ -67,6 +79,11 @@ examples: >> clocks = <&aoss_qmp>; >> clock-names = "apb"; >> >> + interrupts = , >> + ; >> + interrupt-names = "etrirq0", >> + "etrirq1; >> + >> in-ports { >> #address-cells = <1>; >> #size-cells = <0>; >> >> -- >> 2.34.1 >>