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X-CSE-ConnectionGUID: KGAoTxNuSbusOXd9SMGfkg== X-CSE-MsgGUID: hHFS+P8zSdq7w7e3cFtbDA== X-IronPort-AV: E=McAfee;i="6800,10657,11799"; a="92146405" X-IronPort-AV: E=Sophos;i="6.24,172,1774335600"; d="scan'208";a="92146405" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2026 14:34:33 -0700 X-CSE-ConnectionGUID: IDJsD9mQQyeifdLTyyq1CQ== X-CSE-MsgGUID: GNzTjLvoQACC9QqqNZseRQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,172,1774335600"; d="scan'208";a="242510319" Received: from rfrazer-mobl3.amr.corp.intel.com (HELO [10.125.111.23]) ([10.125.111.23]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2026 14:34:32 -0700 Message-ID: Date: Wed, 27 May 2026 14:34:31 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 01/31] cxl/mbox: Flag support for Dynamic Capacity Devices (DCD) To: Anisa Su , linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org Cc: nvdimm@lists.linux.dev, Dan Williams , Jonathan Cameron , Davidlohr Bueso , Vishal Verma , Ira Weiny , Alison Schofield , John Groves , Gregory Price , Ira Weiny References: <4700826deb086665c9e1c643156864eaecfe1fef.1779528761.git.anisa.su@samsung.com> Content-Language: en-US From: Dave Jiang In-Reply-To: <4700826deb086665c9e1c643156864eaecfe1fef.1779528761.git.anisa.su@samsung.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 5/23/26 2:42 AM, Anisa Su wrote: > From: Ira Weiny > > Per the CXL 3.1 specification software must check the Command Effects May as well update to CXL r4.0 > Log (CEL) for dynamic capacity command support. > > Detect support for the DCD commands while reading the CEL, including: > > Get DC Config > Get DC Extent List > Add DC Response > Release DC > > Based on an original patch by Navneet Singh. > > Signed-off-by: Ira Weiny missing Anisa sign off > > --- > Changes: > [anisa: rebase] > --- > drivers/cxl/core/mbox.c | 43 +++++++++++++++++++++++++++++++++++++++++ > drivers/cxl/cxlmem.h | 15 ++++++++++++++ > 2 files changed, 58 insertions(+) > > diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c > index aaa5c6277ebf..7ef5708bf210 100644 > --- a/drivers/cxl/core/mbox.c > +++ b/drivers/cxl/core/mbox.c > @@ -165,6 +165,42 @@ static void cxl_set_security_cmd_enabled(struct cxl_security_state *security, > } > } > > +static bool cxl_is_dcd_command(u16 opcode) > +{ > +#define CXL_MBOX_OP_DCD_CMDS 0x48 > + > + return (opcode >> 8) == CXL_MBOX_OP_DCD_CMDS; > +} > + > +static void cxl_set_dcd_cmd_enabled(struct cxl_memdev_state *mds, u16 opcode, > + unsigned long *cmd_mask) mds not used, consider drop > +{ > + switch (opcode) { > + case CXL_MBOX_OP_GET_DC_CONFIG: > + set_bit(CXL_DCD_ENABLED_GET_CONFIG, cmd_mask); > + break; > + case CXL_MBOX_OP_GET_DC_EXTENT_LIST: > + set_bit(CXL_DCD_ENABLED_GET_EXTENT_LIST, cmd_mask); > + break; > + case CXL_MBOX_OP_ADD_DC_RESPONSE: > + set_bit(CXL_DCD_ENABLED_ADD_RESPONSE, cmd_mask); > + break; > + case CXL_MBOX_OP_RELEASE_DC: > + set_bit(CXL_DCD_ENABLED_RELEASE, cmd_mask); > + break; > + default: > + break; > + } > +} > + > +static bool cxl_verify_dcd_cmds(struct cxl_memdev_state *mds, unsigned long *cmds_seen) mds not used. consider drop > +{ > + DECLARE_BITMAP(all_cmds, CXL_DCD_ENABLED_MAX); > + > + bitmap_fill(all_cmds, CXL_DCD_ENABLED_MAX); > + return bitmap_equal(cmds_seen, all_cmds, CXL_DCD_ENABLED_MAX); Above lines can be replaced with: return bitmap_full(cmds_seen, CXL_DCD_ENABLED_MAX); > +} > + > static bool cxl_is_poison_command(u16 opcode) > { > #define CXL_MBOX_OP_POISON_CMDS 0x43 > @@ -757,6 +793,7 @@ static void cxl_walk_cel(struct cxl_memdev_state *mds, size_t size, u8 *cel) > struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox; > struct cxl_cel_entry *cel_entry; > const int cel_entries = size / sizeof(*cel_entry); > + DECLARE_BITMAP(dcd_cmds, CXL_DCD_ENABLED_MAX); Need to zero out the declared bitmap 'dcd_cmds' on stack before using. DECLARE_BITMAP(dcd_cmds, CXL_DCD_ENABLED_MAX) = {}; > struct device *dev = mds->cxlds.dev; > int i, ro_cmds = 0, wr_cmds = 0; > > @@ -785,11 +822,17 @@ static void cxl_walk_cel(struct cxl_memdev_state *mds, size_t size, u8 *cel) > enabled++; > } > > + if (cxl_is_dcd_command(opcode)) { > + cxl_set_dcd_cmd_enabled(mds, opcode, dcd_cmds); > + enabled++; > + } > + > dev_dbg(dev, "Opcode 0x%04x %s\n", opcode, > enabled ? "enabled" : "unsupported by driver"); > } > > set_features_cap(cxl_mbox, ro_cmds, wr_cmds); > + mds->dcd_supported = cxl_verify_dcd_cmds(mds, dcd_cmds); > } > > static struct cxl_mbox_get_supported_logs *cxl_get_gsl(struct cxl_memdev_state *mds) > diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h > index 776c50d1db51..53444af448d7 100644 > --- a/drivers/cxl/cxlmem.h > +++ b/drivers/cxl/cxlmem.h > @@ -230,6 +230,15 @@ struct cxl_event_state { > struct mutex log_lock; > }; > > +/* Device enabled DCD commands */ > +enum dcd_cmd_enabled_bits { > + CXL_DCD_ENABLED_GET_CONFIG, > + CXL_DCD_ENABLED_GET_EXTENT_LIST, > + CXL_DCD_ENABLED_ADD_RESPONSE, > + CXL_DCD_ENABLED_RELEASE, > + CXL_DCD_ENABLED_MAX > +}; > + would be nice to have comment point to where in the spec this is DJ > /* Device enabled poison commands */ > enum poison_cmd_enabled_bits { > CXL_POISON_ENABLED_LIST, > @@ -405,6 +414,7 @@ static inline struct cxl_dev_state *mbox_to_cxlds(struct cxl_mailbox *cxl_mbox) > * @partition_align_bytes: alignment size for partition-able capacity > * @active_volatile_bytes: sum of hard + soft volatile > * @active_persistent_bytes: sum of hard + soft persistent > + * @dcd_supported: all DCD commands are supported > * @event: event log driver state > * @poison: poison driver state info > * @security: security driver state info > @@ -424,6 +434,7 @@ struct cxl_memdev_state { > u64 partition_align_bytes; > u64 active_volatile_bytes; > u64 active_persistent_bytes; > + bool dcd_supported; > > struct cxl_event_state event; > struct cxl_poison_state poison; > @@ -485,6 +496,10 @@ enum cxl_opcode { > CXL_MBOX_OP_UNLOCK = 0x4503, > CXL_MBOX_OP_FREEZE_SECURITY = 0x4504, > CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505, > + CXL_MBOX_OP_GET_DC_CONFIG = 0x4800, > + CXL_MBOX_OP_GET_DC_EXTENT_LIST = 0x4801, > + CXL_MBOX_OP_ADD_DC_RESPONSE = 0x4802, > + CXL_MBOX_OP_RELEASE_DC = 0x4803, > CXL_MBOX_OP_MAX = 0x10000 > }; >