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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47787e2bcf9sm256771775e9.3.2025.11.16.05.50.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 16 Nov 2025 05:50:51 -0800 (PST) Message-ID: Date: Sun, 16 Nov 2025 13:50:49 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 3/5] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY To: Hangxiang Ma , Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, Jingyi Wang , Atiya Kailany References: <20251113-add-support-for-camss-on-kaanapali-v6-0-1e6038785a8e@oss.qualcomm.com> <20251113-add-support-for-camss-on-kaanapali-v6-3-1e6038785a8e@oss.qualcomm.com> From: Bryan O'Donoghue Content-Language: en-US In-Reply-To: <20251113-add-support-for-camss-on-kaanapali-v6-3-1e6038785a8e@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 14/11/2025 03:29, Hangxiang Ma wrote: > Add more detailed resource information for CSIPHY devices in the camss > driver along with the support for v2.4.0 in the 2 phase CSIPHY driver > that is responsible for the PHY lane register configuration, module > reset and interrupt handling. > > Signed-off-by: Hangxiang Ma > --- > .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 124 +++++++++++++++++++++ > drivers/media/platform/qcom/camss/camss.c | 107 ++++++++++++++++++ > 2 files changed, 231 insertions(+) > > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > index 9b6a0535cdf8..5499f4141294 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > @@ -588,6 +588,123 @@ csiphy_lane_regs lane_regs_sm8550[] = { > {0x0C64, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, > }; > > +/* 3nm 2PH v 2.4.0 2p5Gbps 4 lane DPHY mode */ > +static const struct > +csiphy_lane_regs lane_regs_kaanapali[] = { > + /* LN 0 */ > + {0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0090, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0094, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, > + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0000, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0008, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, > + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL}, > + {0x005C, 0x54, 0x00, CSIPHY_SKEW_CAL}, > + {0x0060, 0xFD, 0x00, CSIPHY_SKEW_CAL}, > + {0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL}, > + > + /* LN 2 */ > + {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0490, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0494, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, > + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0400, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0408, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, > + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL}, > + {0x045C, 0x54, 0x00, CSIPHY_SKEW_CAL}, > + {0x0460, 0xFD, 0x00, CSIPHY_SKEW_CAL}, > + {0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL}, > + > + /* LN 4 */ > + {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0890, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0894, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, > + {0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0800, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0808, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, > + {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL}, > + {0x085C, 0x54, 0x00, CSIPHY_SKEW_CAL}, > + {0x0860, 0xFD, 0x00, CSIPHY_SKEW_CAL}, > + {0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL}, > + > + /* LN 6 */ > + {0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, > + {0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C00, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C38, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, > + {0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C94, 0xD7, 0x00, CSIPHY_SKEW_CAL}, > + {0x0C5C, 0x54, 0x00, CSIPHY_SKEW_CAL}, > + {0x0C60, 0xFD, 0x00, CSIPHY_SKEW_CAL}, > + {0x0C64, 0x7F, 0x00, CSIPHY_SKEW_CAL}, > + > + /* LN CLK */ > + {0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, > + {0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, > + {0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, > +}; > + > /* 4nm 2PH v 2.1.2 2p5Gbps 4 lane DPHY mode */ > static const struct > csiphy_lane_regs lane_regs_x1e80100[] = { > @@ -921,6 +1038,7 @@ static bool csiphy_is_gen2(u32 version) > case CAMSS_845: > case CAMSS_8550: > case CAMSS_8775P: > + case CAMSS_KAANAPALI: > case CAMSS_X1E80100: > ret = true; > break; > @@ -1030,6 +1148,12 @@ static int csiphy_init(struct csiphy_device *csiphy) > regs->lane_regs = &lane_regs_sa8775p[0]; > regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p); > break; > + case CAMSS_KAANAPALI: > + regs->lane_regs = &lane_regs_kaanapali[0]; > + regs->lane_array_size = ARRAY_SIZE(lane_regs_kaanapali); > + regs->offset = 0x1000; > + regs->common_status_offset = 0x138; > + break; > default: > break; > } > diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c > index 658d9c9183d4..b12e79e40e97 100644 > --- a/drivers/media/platform/qcom/camss/camss.c > +++ b/drivers/media/platform/qcom/camss/camss.c > @@ -34,6 +34,111 @@ > > static const struct parent_dev_ops vfe_parent_dev_ops; > > +static const struct camss_subdev_resources csiphy_res_kaanapali[] = { > + /* CSIPHY0 */ > + { > + .regulators = { "vdd-csiphy0-0p8", "vdd-csiphy0-1p2" }, > + .clock = { "csiphy0", "csiphy0_timer", > + "cam_top_ahb", "cam_top_fast_ahb" }, > + .clock_rate = { { 400000000, 480000000 }, > + { 400000000 }, > + { 0 }, > + { 0 } }, > + .reg = { "csiphy0" }, > + .interrupt = { "csiphy0" }, > + .csiphy = { > + .id = 0, > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sdm845 > + } > + }, > + /* CSIPHY1 */ > + { > + .regulators = { "vdd-csiphy1-0p8", "vdd-csiphy1-1p2" }, > + .clock = { "csiphy1", "csiphy1_timer", > + "cam_top_ahb", "cam_top_fast_ahb" }, > + .clock_rate = { { 400000000, 480000000 }, > + { 400000000 }, > + { 0 }, > + { 0 } }, > + .reg = { "csiphy1" }, > + .interrupt = { "csiphy1" }, > + .csiphy = { > + .id = 1, > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sdm845 > + } > + }, > + /* CSIPHY2 */ > + { > + .regulators = { "vdd-csiphy2-0p8", "vdd-csiphy2-1p2" }, > + .clock = { "csiphy2", "csiphy2_timer", > + "cam_top_ahb", "cam_top_fast_ahb" }, > + .clock_rate = { { 400000000, 480000000 }, > + { 400000000 }, > + { 0 }, > + { 0 } }, > + .reg = { "csiphy2" }, > + .interrupt = { "csiphy2" }, > + .csiphy = { > + .id = 2, > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sdm845 > + } > + }, > + /* CSIPHY3 */ > + { > + .regulators = { "vdd-csiphy3-0p8", "vdd-csiphy3-1p2" }, > + .clock = { "csiphy3", "csiphy3_timer", > + "cam_top_ahb", "cam_top_fast_ahb" }, > + .clock_rate = { { 400000000, 480000000 }, > + { 400000000 }, > + { 0 }, > + { 0 } }, > + .reg = { "csiphy3" }, > + .interrupt = { "csiphy3" }, > + .csiphy = { > + .id = 3, > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sdm845 > + } > + }, > + /* CSIPHY4 */ > + { > + .regulators = { "vdd-csiphy4-0p8", "vdd-csiphy4-1p2" }, > + .clock = { "csiphy4", "csiphy4_timer", > + "cam_top_ahb", "cam_top_fast_ahb" }, > + .clock_rate = { { 400000000, 480000000 }, > + { 400000000 }, > + { 0 }, > + { 0 } }, > + .reg = { "csiphy4" }, > + .interrupt = { "csiphy4" }, > + .csiphy = { > + .id = 4, > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sdm845 > + } > + }, > + /* CSIPHY5 */ > + { > + .regulators = { "vdd-csiphy5-0p8", "vdd-csiphy5-1p2" }, > + .clock = { "csiphy5", "csiphy5_timer", > + "cam_top_ahb", "cam_top_fast_ahb" }, > + .clock_rate = { { 400000000, 480000000 }, > + { 400000000 }, > + { 0 }, > + { 0 } }, > + .reg = { "csiphy5" }, > + .interrupt = { "csiphy5" }, > + .csiphy = { > + .id = 5, > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sdm845 > + } > + }, > +}; > + > static const struct resources_icc icc_res_kaanapali[] = { > { > .name = "ahb", > @@ -4308,8 +4413,10 @@ static void camss_remove(struct platform_device *pdev) > static const struct camss_resources kaanapali_resources = { > .version = CAMSS_KAANAPALI, > .pd_name = "top", > + .csiphy_res = csiphy_res_kaanapali, > .icc_res = icc_res_kaanapali, > .icc_path_num = ARRAY_SIZE(icc_res_kaanapali), > + .csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali), > }; > > static const struct camss_resources msm8916_resources = { > Reviewed-by: Bryan O'Donoghue