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Thu, 3 Jul 2025 00:53:44 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 3 Jul 2025 00:53:43 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 3 Jul 2025 00:53:43 -0500 Received: from [172.24.227.38] (ula0502350.dhcp.ti.com [172.24.227.38]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5635rbEP579551; Thu, 3 Jul 2025 00:53:38 -0500 Message-ID: Date: Thu, 3 Jul 2025 11:23:37 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 1/4] arm64: dts: ti: Add bootph property to nodes at source for am62a To: Bryan Brattlof CC: , , , , , , , , , , , , , , , References: <20250627115753.2246881-1-p-bhagat@ti.com> <20250627115753.2246881-2-p-bhagat@ti.com> <20250701160828.lmmfgfrmfcqiwpzz@bryanbrattlof.com> Content-Language: en-US From: Paresh Bhagat In-Reply-To: <20250701160828.lmmfgfrmfcqiwpzz@bryanbrattlof.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Hi Bryan, On 01/07/25 21:38, Bryan Brattlof wrote: > On June 27, 2025 thus sayeth Paresh Bhagat: >> Add bootph property directly into the original definitions of relevant >> nodes (e.g., power domains, USB controllers, and other peripherals) >> within their respective DTSI files (ex. main, mcu, and wakeup) for >> am62a. >> >> By defining bootph in the nodes source definitions instead of appending >> it later in final DTS files, this change ensures that the property is >> inherently present wherever the nodes are reused across derived device >> trees. >> >> Signed-off-by: Paresh Bhagat >> --- >> arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 14 ++++++++++++++ >> arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 1 + >> arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 2 ++ >> 3 files changed, 17 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi >> index 63e097ddf988..770f1258b0aa 100644 >> --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi >> > ... > >> main_pmx0: pinctrl@f4000 { >> @@ -262,6 +271,7 @@ main_pmx0: pinctrl@f4000 { >> #pinctrl-cells = <1>; >> pinctrl-single,register-width = <32>; >> pinctrl-single,function-mask = <0xffffffff>; >> + bootph-all; >> }; > I don't think the boot phase flags for the pinmux nodes need to be here. > The child nodes for the MMC, UART and Ethernet pins should take care of > this. > > ... > >> diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi >> b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi >> index ee961ced7208..df4aa131097f 100644 >> --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi >> @@ -12,6 +12,7 @@ mcu_pmx0: pinctrl@4084000 { >> #pinctrl-cells = <1>; >> pinctrl-single,register-width = <32>; >> pinctrl-single,function-mask = <0xffffffff>; >> + bootph-all; >> }; > Same here. If we need any pins from the MCU domain during bootup those > nodes can take care of adding the boot phase flag. > > ~Bryan Will fix this thanks.