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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA4MDIyMyBTYWx0ZWRfXzdVoerWZagCp Rxf76DiatKrkWKybXrAtG8RTIEuMs58sOeQKEpiSrAxEFFWJ7MtI/Rc+1IWeGls949vBEFLYjXs hQU6bWCUd1HNfeNr/Yjz9zkePurbTQA= X-Proofpoint-ORIG-GUID: jyxJcf733YriW3qgE06E7w2VEzcyRk7h X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA4MDIyMyBTYWx0ZWRfXzNzBfPHyjYsr TjnS5EKMdC8KiT1QOJBGUKzs1XDsvl+yQb7PSQryXGd7BLbRdacMhP7wuHzQEGZQNUsufolMqGB csTvTzZhtUw8xVctwqNNn22i4ERwqUzvRQb7GPkBs2FR2HNwCq8cYPeTuirz7S3T85JJzR66cow uinmTTSlqpsopZxAVrvdfHiNJPMTHanvIa/TPzoWDQnOS46EzYavydBpKuaffgITF8ImgnwqHeZ QpcX3xiIWipNl8kzROnIoJiatZAi1Zt/AEXwkuaGZ5L597V/knkb0pWXRT3lxqeEefCZbkCKG6a j95rbhjeM5TaRL+rULV1NcbtKVW+pi/GoWnSM+ByXri31KOk3SOGdG/3rCqkgq/cEnQuedq31UG 7DcfCUjs24IUCjRxpPRflOvepR2pSzU5ipz5mmeKvuWhuTDdjlPchCwuw7qD8gw3U96y7k3jfem k6UpB6KSoNhIATzBJ5w== X-Authority-Analysis: v=2.4 cv=Xey5Co55 c=1 sm=1 tr=0 ts=6aa0702a cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=ZsC4DHZuhs/kKio7QBcDoQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=G3gKnUrgdjqRGvMogNIA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-GUID: jyxJcf733YriW3qgE06E7w2VEzcyRk7h X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-08_03,2026-09-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609080223 On 8/31/26 7:33 AM, Sarath Ganapathiraju via B4 Relay wrote: > From: Sarath Ganapathiraju > > The HeartBeat Pulse (also known as RateGen Pulse) synchronizes the > start of the DMAs and Codec Interfaces for the audio usecases and can > serve as a periodic wakeup source for the DSP. > > Add the LPASS VA CSR driver that models the rate generator as a clock > provider so it is enabled and disabled automatically alongside the other > clocks during runtime PM resume and suspend. > > Reviewed-by: Prasad Kumpatla > Tested-by: Prasad Kumpatla > Signed-off-by: Sarath Ganapathiraju > --- > drivers/clk/qcom/Kconfig | 14 ++++ > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/lpass-va-csr.c | 148 ++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 163 insertions(+) > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index e609a7819e07..502acd86efd6 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -2105,6 +2105,20 @@ config CLK_GFM_LPASS_SM8250 > Support for the Glitch Free Mux (GFM) Low power audio > subsystem (LPASS) clocks found on SM8250 SoCs. > > +config QCOM_CLK_LPASS_HEARTBEAT_PULSE > + tristate "Qualcomm LPASS VA CSR heartbeat pulse clock provider" > + depends on COMMON_CLK > + depends on ARM64 || COMPILE_TEST > + select REGMAP_MMIO > + default m if ARCH_QCOM > + help > + Qualcomm LPASS VA CSR block contains the rate generator hardware > + that produces the HeartBeat Pulse (also known as RateGen Pulse). > + This driver models the rate generator as a clock provider so > + that consumers can enable or disable it via the common clock > + framework, and it can be used to synchronize the start of DMAs > + and Codec Interfaces or as a periodic wakeup source for the DSP. > + > config SM_VIDEOCC_8450 > tristate "SM8450 Video Clock Controller" > depends on ARM64 || COMPILE_TEST > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index b8590963736a..3f6a52cc7ec7 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_ELIZA_GPUCC) += gpucc-eliza.o > obj-$(CONFIG_CLK_ELIZA_TCSRCC) += tcsrcc-eliza.o > obj-$(CONFIG_CLK_ELIZA_VIDEOCC) += videocc-eliza.o > obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o > +obj-$(CONFIG_QCOM_CLK_LPASS_HEARTBEAT_PULSE) += lpass-va-csr.o > obj-$(CONFIG_CLK_GLYMUR_CAMCC) += camcc-glymur.o > obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o > obj-$(CONFIG_CLK_GLYMUR_EVACC) += evacc-glymur.o > diff --git a/drivers/clk/qcom/lpass-va-csr.c b/drivers/clk/qcom/lpass-va-csr.c > new file mode 100644 > index 000000000000..8438d000814e > --- /dev/null > +++ b/drivers/clk/qcom/lpass-va-csr.c > @@ -0,0 +1,148 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include ... > + > +#define to_lpass_va_csr(_hw) container_of(_hw, struct lpass_va_csr, hb_hw) > + > +static int heartbeat_pulse_prepare(struct clk_hw *hw) > +{ > + struct lpass_va_csr *csr = to_lpass_va_csr(hw); > + int ret; > + > + ret = regmap_write(csr->regmap, LPASS_RATE_GEN_COUNTER_0, csr->data->counter_0); > + if (ret) > + return ret; > + > + ret = regmap_write(csr->regmap, LPASS_RATE_GEN_DELAY, csr->data->delay); > + if (ret) > + return ret; Does these two registers need to be written on every prepare? if we need to program just once then we can just use clk_regmap_gate_ops which will implement pretty much the same driver. > + > + return regmap_set_bits(csr->regmap, LPASS_RATE_GEN_CTRL, LPASS_RG_CTRL_EN); > +} > + > +static void heartbeat_pulse_unprepare(struct clk_hw *hw) > +{ > + struct lpass_va_csr *csr = to_lpass_va_csr(hw); > + > + regmap_clear_bits(csr->regmap, LPASS_RATE_GEN_CTRL, LPASS_RG_CTRL_EN); > +} > + > +static int heartbeat_pulse_is_prepared(struct clk_hw *hw) > +{ > + struct lpass_va_csr *csr = to_lpass_va_csr(hw); > + > + return regmap_test_bits(csr->regmap, LPASS_RATE_GEN_CTRL, LPASS_RG_CTRL_EN); > +} > + > +static const struct clk_ops heartbeat_pulse_ops = { > + .prepare = heartbeat_pulse_prepare, > + .unprepare = heartbeat_pulse_unprepare, > + .is_prepared = heartbeat_pulse_is_prepared, > +}; > + > +static int lpass_va_csr_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct lpass_va_csr *csr; > + struct clk_init_data init = { > + .name = "lpass_heartbeat_pulse", > + .ops = &heartbeat_pulse_ops, > + }; > + void __iomem *base; > + int ret; > + > + csr = devm_kzalloc(dev, sizeof(*csr), GFP_KERNEL); > + if (!csr) > + return -ENOMEM; > + > + csr->data = of_device_get_match_data(dev); > + if (!csr->data) This check will never fail as the device gets only probed if compatible matches. > + return dev_err_probe(dev, -EINVAL, "no variant data for compatible\n"); > + > + base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(base)) > + return PTR_ERR(base); > +