From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: * X-Spam-Status: No, score=1.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, RDNS_NONE,SPF_HELO_NONE,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from foss.arm.com ([217.140.110.172]:51138 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729742AbgCKPrQ (ORCPT ); Wed, 11 Mar 2020 11:47:16 -0400 Subject: Re: [PATCH] ARM: dts: dra7: Add bus_dma_limit for L3 bus To: Tony Lindgren , Roger Quadros Cc: Tero Kristo , hch@lst.de, robh+dt@kernel.org, nm@ti.com, nsekhar@ti.com, linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20200310115309.31354-1-rogerq@ti.com> <20200310154829.GS37466@atomide.com> <20200311152347.GW37466@atomide.com> From: Robin Murphy Message-ID: Date: Wed, 11 Mar 2020 15:47:12 +0000 MIME-Version: 1.0 In-Reply-To: <20200311152347.GW37466@atomide.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: On 11/03/2020 3:23 pm, Tony Lindgren wrote: > * Roger Quadros [200311 07:21]: >> >> >> On 10/03/2020 17:48, Tony Lindgren wrote: >>> * Tero Kristo [200310 14:46]: >>>> On 10/03/2020 13:53, Roger Quadros wrote: >>>>> The L3 interconnect can access only 32-bits of address. >>>>> Add the dma-ranges property to reflect this limit. >>>>> >>>>> This will ensure that no device under L3 is >>>>> given > 32-bit address for DMA. >>>>> >>>>> Issue was observed only with SATA on DRA7-EVM with 4GB RAM >>>>> and CONFIG_ARM_LPAE enabled. This is because the controller >>>>> can perform 64-bit DMA and was setting the dma_mask to 64-bit. >>>>> >>>>> Setting the correct bus_dma_limit fixes the issue. >>>> >>>> This seems kind of messy to modify almost every DT node because of this.... >>>> Are you sure this is the only way to get it done? No way to modify the sata >>>> node only which is impacted somehow? >>>> >>>> Also, what if you just pass 0xffffffff to the dma-ranges property? That >>>> would avoid modifying every node I guess. >>> >>> Also, I think these interconnects are not limited to 32-bit access. >> >> But from Table 2-1. L3_MAIN Memory Map >> >> Start address 0x0000_0000 >> End address 0xFFFF_FFFF >> >> So it is 32-bit limit, right? > > Hmm so what war Robin saying earlier that DMA access seems to be > limited to lower 2GB only though? That's the lower 2GB *of DRAM*, which occupies the upper 2GB of the L3 memory map ;) Robin.