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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae6e7ee44d4sm1175223766b.39.2025.07.16.03.33.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Jul 2025 03:33:50 -0700 (PDT) Message-ID: Date: Wed, 16 Jul 2025 12:33:48 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] PCI: qcom: Move qcom_pcie_icc_opp_update() to notifier callback To: Manivannan Sadhasivam Cc: Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold , Krishna Chaitanya Chundru References: <20250714-aspm_fix-v1-0-7d04b8c140c8@oss.qualcomm.com> <20250714-aspm_fix-v1-2-7d04b8c140c8@oss.qualcomm.com> <55f2e014-044c-4021-8b01-99bdf2a0fd7f@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE2MDA5MyBTYWx0ZWRfX1kWViZTh2XZM i/29UgD+8zU4EnVJx/+m+YZuz3iZClJE4bmsadg/TN2G6Tf/w75NU9hflmqKJ80L26tfvvjdCeu yc3J4Aoztr79futIx6WZ5IkzeCrng8bpAcWAmUQxRGoy0QUDl9cp/T9retWBSPVg+G3cP3LCcNe OqbJSZz7fqapcdpXcw9UyLOVHLWGa64skw2dYuKaUxu9cmLt1+cgGxn2I5fIc3IsQEHCbN0u8x+ 9xhODOhLCsIsg9oxiPRenctAfjuSL4XfJ0oA3nY0elymMoJMCy+3JhDf+8aM53yUjNn0RgISxHN Bp9yBv9Nvlo+4U8rCnTaJBbRi2/YKkvZ+SOLqJKxfdptregRLBdBy78xZ5KXyiNPIRFH9wfr6od hIdNXZA+yKywgodiKUC/oeljOxXI+VoJ9VqzlNMUzwkJc1u+sMTxxa0UQ0IMovnC2BTvf8Z3 X-Proofpoint-ORIG-GUID: V4-U0yKbpWBNkoshg3jOrGN1yXgGOzbj X-Proofpoint-GUID: V4-U0yKbpWBNkoshg3jOrGN1yXgGOzbj X-Authority-Analysis: v=2.4 cv=f59IBPyM c=1 sm=1 tr=0 ts=68778010 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=EnMyU6b1km1a4ziX4qoA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-16_01,2025-07-15_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 spamscore=0 mlxscore=0 bulkscore=0 suspectscore=0 impostorscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507160093 On 7/16/25 7:28 AM, Manivannan Sadhasivam wrote: > On Tue, Jul 15, 2025 at 12:45:36PM GMT, Konrad Dybcio wrote: >> On 7/15/25 12:36 PM, Manivannan Sadhasivam wrote: >>> On Tue, Jul 15, 2025 at 11:54:48AM GMT, Konrad Dybcio wrote: >>>> On 7/14/25 8:01 PM, Manivannan Sadhasivam wrote: >>>>> It allows us to group all the settings that need to be done when a PCI >>>>> device is attached to the bus in a single place. >>>>> >>>>> Signed-off-by: Manivannan Sadhasivam >>>>> --- [...] >>> Let me think of other ways to call these two APIs during the device addition. If >>> there are no sane ways, I'll drop *this* patch. >> >> Would it be too naive to assume BUS_NOTIFY_ADD_DEVICE is a good fit? > > BUS_NOTIFY_ADD_DEVICE is not currently a good fit as ASPM link state > initialization happen after all the devices are enumerated for the slot. This is > something to be fixed in the PCI core and would allow us to use > BUS_NOTIFY_ADD_DEVICE. > > I talked to Bjorn H and we both agreed that this needs to be revisited. But I'm > just worrried that until this happens, we cannot upstream the ASPM fix and not > even backport it to 6.16/16. > > So maybe we need to resort to this patch as an interim fix if everyone agrees. I'm not opposed if there's going to be an improved solution next cycle. Having ASPM 99.9% of the time is much better than not having it at all > >> Do >> ASPM setting need to be reapplied after the PCIe device is reset? (well >> I would assume there are probably multiple levels of "reset" :/) >> > > I'm assuming that you are referring to link down reset here. PCI core takes care > of saving both the endpoint as well as Root Port config space when that happens > and restores them afterwards. Nice, thanks for confirming Konrad