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([2a01:e0a:106d:1080:9476:5165:3a16:262]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e71b789ecsm19170893f8f.29.2026.11.02.05.00.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Nov 2026 05:00:58 -0800 (PST) Message-ID: Date: Mon, 2 Nov 2026 14:00:57 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: Neil Armstrong Subject: Re: [PATCH v2 1/5] drm/panel: feiyang-fy07024di26a30d: Fix prepare error cleanup To: Hsieh Hung-En , dianders@chromium.org, jesszhan0024@gmail.com Cc: jagan@amarulasolutions.com, osama.abdelkader@gmail.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch References: <20261102043215.990351-1-hungen3108@gmail.com> <20261102043215.990351-2-hungen3108@gmail.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20261102043215.990351-2-hungen3108@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 11/2/26 05:32, Hsieh Hung-En wrote: > feiyang_prepare() returns without disabling previously enabled > regulators if enabling AVDD or writing DCS commands fails. Since > drm_panel_prepare() does not mark the panel as prepared on failure, > drm_panel_unprepare() does not call the driver's unprepare() callback, > leaving regulator enable counts elevated even after subsequent > successful prepare/unprepare cycles. > > Disable DVDD if enabling AVDD fails. On a DCS write failure, restore > the reset GPIO to its unprepared state and disable both regulators, > preserving the existing 10 ms power-off interval between AVDD and DVDD. > > Fixes: 69dc678abc2b ("drm/panel: Add Feiyang FY07024DI26A30-D MIPI-DSI LCD panel") > Reported-by: Douglas Anderson > Closes: https://lore.kernel.org/r/CAD=FV=Xm48DUT==8HuuGCSFZtLTEk-W2Q6UTfqt-MnM4nULzTw@mail.gmail.com > Signed-off-by: Hsieh Hung-En > --- > > Notes: > Power sequencing note: > > The error path retains the 10 ms AVDD-to-DVDD shutdown interval > used by unprepare(). > > The FY07024DI26A30-D datasheet, Section 7.3 (Power, Signal sequence), > specifies T10 > 0 between AVDD/VGL reaching GND and DVDD starting > to fall. The delay allows time for AVDD to discharge before disabling > DVDD, but compliance with T10 has not been verified on hardware. > > The existing unprepare() comment associates the delay with T11, > which actually specifies the DVDD fall time (0 < T11 <= 10 ms). > That comment can be corrected separately. > > The msleep(10) checkpatch warning is expected. T10 has no specified > upper bound, so a longer sleep does not violate that timing constraint. > msleep() is retained to match the existing unprepare() sequence. > > Datasheet: > https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf > > .../gpu/drm/panel/panel-feiyang-fy07024di26a30d.c | 15 +++++++++++++-- > 1 file changed, 13 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c b/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c > index c1d8ca5ca6e1..bb4cc1ea2ece 100644 > --- a/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c > +++ b/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c > @@ -59,7 +59,7 @@ static int feiyang_prepare(struct drm_panel *panel) > > ret = regulator_enable(ctx->avdd); > if (ret) > - return ret; > + goto disable_dvdd; > > /* T3 (dvdd rise + avdd start + avdd rise) T3 >= 20ms */ > msleep(20); > @@ -84,10 +84,21 @@ static int feiyang_prepare(struct drm_panel *panel) > ret = mipi_dsi_dcs_write_buffer(dsi, cmd->data, > FEIYANG_INIT_CMD_LEN); > if (ret < 0) > - return ret; > + goto assert_reset; > } > > return 0; > + > +assert_reset: > + gpiod_set_value(ctx->reset, 0); > + regulator_disable(ctx->avdd); > + > + /* Preserve the AVDD-to-DVDD shutdown delay from unprepare(). */ > + msleep(10); > + > +disable_dvdd: > + regulator_disable(ctx->dvdd); > + return ret; > } > > static int feiyang_enable(struct drm_panel *panel) Reviewed-by: Neil Armstrong Thanks, Neil