From: Florian Fainelli <f.fainelli@gmail.com>
To: linux-mips@vger.kernel.org
Cc: "Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
"Paul Burton" <paulburton@kernel.org>,
"Paul Cercueil" <paul@crapouillou.net>,
"Stephen Boyd" <sboyd@kernel.org>,
"Brian Masney" <bmasney+clk@redhat.com>,
"Jerome Brunet" <jbrunet+clk@baylibre.com>,
"周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"open list" <linux-kernel@vger.kernel.org>,
"open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>,
hns@goldelico.com, paul@boddie.org.uk
Subject: Re: [PATCH v5 2/4] MIPS: Skip generic IPI setup for platform-specific callbacks
Date: Fri, 13 Nov 2026 10:43:42 -0800 [thread overview]
Message-ID: <e068c222-eec8-4dcc-bf7e-d91ae2ef175b@gmail.com> (raw)
In-Reply-To: <20261113184210.470320-3-f.fainelli@gmail.com>
On 11/13/26 10:42, Florian Fainelli wrote:
> A generic MIPS kernel can select a platform SMP backend with direct IPI
> callbacks instead of an IPI IRQ domain. The XBurst backend uses CP0
> mailboxes, so generic IPI allocation would find no domain and BUG when
> more than one CPU is present.
>
> Skip generic IPI initialization when neither selected send callback uses
> the generic implementation. Keep initialization when either callback
> uses generic IRQ IPIs, and retain the existing single-CPU shortcut.
>
> Sashiko AI reported the XBurst integration issue; Codex assisted with
> the change and extracted-function/build checks.
Argh sorry I missed adding my Signed-off-by tag here..
--
Florian
next prev parent reply other threads:[~2026-11-13 18:43 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-13 18:42 [PATCH v5 0/4] MIPS: CI20: Enable SMP with two CPUs Florian Fainelli
2026-11-13 18:42 ` [PATCH v5 1/4] clk: ingenic: Poll JZ4780 CPU1 power status atomically Florian Fainelli
2026-11-13 18:42 ` [PATCH v5 2/4] MIPS: Skip generic IPI setup for platform-specific callbacks Florian Fainelli
2026-11-13 18:43 ` Florian Fainelli [this message]
2026-11-13 18:42 ` [PATCH v5 3/4] MIPS: Ingenic: Add XBurst SMP support Florian Fainelli
2026-11-13 18:42 ` [PATCH v5 4/4] MIPS: CI20: Enable SMP with two CPUs Florian Fainelli
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