From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from va-1-15.ptr.blmpb.com (va-1-15.ptr.blmpb.com [209.127.230.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B98120CCDC for ; Wed, 25 Jun 2025 07:56:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.127.230.15 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750838183; cv=none; b=r9TN3Olh3MZWh/YwC0WA3WL2MJEI2FUEGUFbKSu/mS+ZSctxOVuh4SdFeK8S4UCPrnX0S+SCeFglHMFe1Cng8A+haR42K2+tZf3kH1G36SoxzCvFBrVBVqpgQ30MRSUNNFBRaGvCj8dmxpxnGqMb+gfXyoEJ8H6oZbpOSe4bHco= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750838183; c=relaxed/simple; bh=hW3k6z49kKwNRejfAMcgIdFU5548Dv/b8lnlYkL2ZcM=; h=From:Date:References:Message-Id:To:Cc:Subject:Content-Type: In-Reply-To:Mime-Version; b=O/bsMPRYVoGrRUhWIyx3jj+14Upx79TuA1B+nXevH98b7HElkneweOBxGSW7vzrxa9Viu0bvsXazSYoD97YXDzYCd+5n70m8iCXHzJSHQtvN9863xlSMjccW/tNKrk/fhZE/Pfle+fWVxusQrhKn1sOsIYy7WmX+MDzZsyFyF60= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=lanxincomputing.com; spf=pass smtp.mailfrom=lanxincomputing.com; dkim=pass (2048-bit key) header.d=lanxincomputing-com.20200927.dkim.feishu.cn header.i=@lanxincomputing-com.20200927.dkim.feishu.cn header.b=mBTR6Pgj; arc=none smtp.client-ip=209.127.230.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=lanxincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lanxincomputing.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=lanxincomputing-com.20200927.dkim.feishu.cn header.i=@lanxincomputing-com.20200927.dkim.feishu.cn header.b="mBTR6Pgj" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=s1; d=lanxincomputing-com.20200927.dkim.feishu.cn; t=1750838130; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=Uwcz+ylJEsmNE1CVgp+CscW5a5nPPX8eXKPrXaxr/uc=; b=mBTR6PgjmCU+frhNcEwLlXR8N78NYFR8ZiLbDiT1l99f1D6q6v6n28ASL4Jth+22MTKN5R od9MIDiPk92CTCB68s4YSWslGs0z5R/hFySbeZxwLvuaA3lIJDCkijGpShrs008oP1ZYLG Ty0N2gbiXvW57po93CoX3okpkXIZJgImBlZKD0npBeUS/nwMQgG35eHcRakGfSQ6zeabf+ LiUXO0kpinv+JCj3aRVRGSWA3RzORVORACUy6QXDZ5+cbehoAIcoIv1wU5oFDLxZjQdyXG BaN2X0DNNaLwAL4HmPkzfS1Ap2yU29Wz5a+a06BUMlvWjfnIHRHQWYTrW0txfg== From: "Nutty Liu" Date: Wed, 25 Jun 2025 15:55:25 +0800 Content-Transfer-Encoding: 7bit Content-Language: en-US References: <20250618113532.471448-1-apatel@ventanamicro.com> <20250618113532.471448-11-apatel@ventanamicro.com> Message-Id: To: "Anup Patel" , "Atish Patra" Cc: "Palmer Dabbelt" , "Paul Walmsley" , "Alexandre Ghiti" , "Andrew Jones" , "Anup Patel" , , , , , "Atish Patra" Subject: Re: [PATCH v3 10/12] RISC-V: KVM: Add vmid field to struct kvm_riscv_hfence Content-Type: text/plain; charset=UTF-8 In-Reply-To: <20250618113532.471448-11-apatel@ventanamicro.com> User-Agent: Mozilla Thunderbird Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 X-Original-From: Nutty Liu Received: from [127.0.0.1] ([139.226.59.215]) by smtp.feishu.cn with ESMTPS; Wed, 25 Jun 2025 15:55:27 +0800 X-Lms-Return-Path: On 6/18/2025 7:35 PM, Anup Patel wrote: > Currently, the struct kvm_riscv_hfence does not have vmid field > and various hfence processing functions always pick vmid assigned > to the guest/VM. This prevents us from doing hfence operation on > arbitrary vmid hence add vmid field to struct kvm_riscv_hfence > and use it wherever applicable. > > Reviewed-by: Atish Patra > Signed-off-by: Anup Patel > --- > arch/riscv/include/asm/kvm_tlb.h | 1 + > arch/riscv/kvm/tlb.c | 30 ++++++++++++++++-------------- > 2 files changed, 17 insertions(+), 14 deletions(-) > > diff --git a/arch/riscv/include/asm/kvm_tlb.h b/arch/riscv/include/asm/kvm_tlb.h > index cd00c9a46cb1..f67e03edeaec 100644 > --- a/arch/riscv/include/asm/kvm_tlb.h > +++ b/arch/riscv/include/asm/kvm_tlb.h > @@ -19,6 +19,7 @@ enum kvm_riscv_hfence_type { > struct kvm_riscv_hfence { > enum kvm_riscv_hfence_type type; > unsigned long asid; > + unsigned long vmid; > unsigned long order; > gpa_t addr; > gpa_t size; > diff --git a/arch/riscv/kvm/tlb.c b/arch/riscv/kvm/tlb.c > index 6fc4361c3d75..349fcfc93f54 100644 > --- a/arch/riscv/kvm/tlb.c > +++ b/arch/riscv/kvm/tlb.c > @@ -237,49 +237,43 @@ static bool vcpu_hfence_enqueue(struct kvm_vcpu *vcpu, > > void kvm_riscv_hfence_process(struct kvm_vcpu *vcpu) > { > - unsigned long vmid; > struct kvm_riscv_hfence d = { 0 }; > - struct kvm_vmid *v = &vcpu->kvm->arch.vmid; > > while (vcpu_hfence_dequeue(vcpu, &d)) { > switch (d.type) { > case KVM_RISCV_HFENCE_UNKNOWN: > break; > case KVM_RISCV_HFENCE_GVMA_VMID_GPA: > - vmid = READ_ONCE(v->vmid); > if (kvm_riscv_nacl_available()) > - nacl_hfence_gvma_vmid(nacl_shmem(), vmid, > + nacl_hfence_gvma_vmid(nacl_shmem(), d.vmid, > d.addr, d.size, d.order); > else > - kvm_riscv_local_hfence_gvma_vmid_gpa(vmid, d.addr, > + kvm_riscv_local_hfence_gvma_vmid_gpa(d.vmid, d.addr, > d.size, d.order); > break; > case KVM_RISCV_HFENCE_VVMA_ASID_GVA: > kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD); > - vmid = READ_ONCE(v->vmid); > if (kvm_riscv_nacl_available()) > - nacl_hfence_vvma_asid(nacl_shmem(), vmid, d.asid, > + nacl_hfence_vvma_asid(nacl_shmem(), d.vmid, d.asid, > d.addr, d.size, d.order); > else > - kvm_riscv_local_hfence_vvma_asid_gva(vmid, d.asid, d.addr, > + kvm_riscv_local_hfence_vvma_asid_gva(d.vmid, d.asid, d.addr, > d.size, d.order); > break; > case KVM_RISCV_HFENCE_VVMA_ASID_ALL: > kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD); > - vmid = READ_ONCE(v->vmid); > if (kvm_riscv_nacl_available()) > - nacl_hfence_vvma_asid_all(nacl_shmem(), vmid, d.asid); > + nacl_hfence_vvma_asid_all(nacl_shmem(), d.vmid, d.asid); > else > - kvm_riscv_local_hfence_vvma_asid_all(vmid, d.asid); > + kvm_riscv_local_hfence_vvma_asid_all(d.vmid, d.asid); > break; > case KVM_RISCV_HFENCE_VVMA_GVA: > kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_RCVD); > - vmid = READ_ONCE(v->vmid); > if (kvm_riscv_nacl_available()) > - nacl_hfence_vvma(nacl_shmem(), vmid, > + nacl_hfence_vvma(nacl_shmem(), d.vmid, > d.addr, d.size, d.order); > else > - kvm_riscv_local_hfence_vvma_gva(vmid, d.addr, > + kvm_riscv_local_hfence_vvma_gva(d.vmid, d.addr, > d.size, d.order); > break; > default: > @@ -336,10 +330,12 @@ void kvm_riscv_hfence_gvma_vmid_gpa(struct kvm *kvm, > gpa_t gpa, gpa_t gpsz, > unsigned long order) > { > + struct kvm_vmid *v = &kvm->arch.vmid; > struct kvm_riscv_hfence data; > > data.type = KVM_RISCV_HFENCE_GVMA_VMID_GPA; > data.asid = 0; > + data.vmid = READ_ONCE(v->vmid); > data.addr = gpa; > data.size = gpsz; > data.order = order; > @@ -359,10 +355,12 @@ void kvm_riscv_hfence_vvma_asid_gva(struct kvm *kvm, > unsigned long gva, unsigned long gvsz, > unsigned long order, unsigned long asid) > { > + struct kvm_vmid *v = &kvm->arch.vmid; > struct kvm_riscv_hfence data; > > data.type = KVM_RISCV_HFENCE_VVMA_ASID_GVA; > data.asid = asid; > + data.vmid = READ_ONCE(v->vmid); > data.addr = gva; > data.size = gvsz; > data.order = order; > @@ -374,10 +372,12 @@ void kvm_riscv_hfence_vvma_asid_all(struct kvm *kvm, > unsigned long hbase, unsigned long hmask, > unsigned long asid) > { > + struct kvm_vmid *v = &kvm->arch.vmid; > struct kvm_riscv_hfence data; > > data.type = KVM_RISCV_HFENCE_VVMA_ASID_ALL; > data.asid = asid; > + data.vmid = READ_ONCE(v->vmid); > data.addr = data.size = data.order = 0; > make_xfence_request(kvm, hbase, hmask, KVM_REQ_HFENCE, > KVM_REQ_HFENCE_VVMA_ALL, &data); > @@ -388,10 +388,12 @@ void kvm_riscv_hfence_vvma_gva(struct kvm *kvm, > unsigned long gva, unsigned long gvsz, > unsigned long order) > { > + struct kvm_vmid *v = &kvm->arch.vmid; > struct kvm_riscv_hfence data; > > data.type = KVM_RISCV_HFENCE_VVMA_GVA; > data.asid = 0; > + data.vmid = READ_ONCE(v->vmid); > data.addr = gva; > data.size = gvsz; > data.order = order; Reviewed-by: Nutty Liu Thanks, Nutty