From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Thippeswamy Havalige <thippeswamy.havalige@amd.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org
Cc: bhelgaas@google.com, michals@xilinx.com, robh+dt@kernel.org,
bharat.kumar.gogada@amd.com
Subject: Re: [PATCH 1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge
Date: Wed, 19 Oct 2022 11:11:24 -0400 [thread overview]
Message-ID: <e077ae19-7271-19a4-e10f-1c7d26b0b304@linaro.org> (raw)
In-Reply-To: <20221019144640.9458-1-thippeswamy.havalige@amd.com>
On 19/10/2022 10:46, Thippeswamy Havalige wrote:
> Convert to YAML dtschemas of Xilinx AXI PCIe Root Port Bridge
> dt binding.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - ranges
> + - device_type
Drop all properties which are already required by referenced schemas.
> + - interrupt-map
> + - "#interrupt-cells"
> + - interrupt-controller
> +
Best regards,
Krzysztof
prev parent reply other threads:[~2022-10-19 15:19 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-19 14:46 Thippeswamy Havalige
2022-10-19 14:46 ` [PATCH 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL " Thippeswamy Havalige
2022-10-19 15:13 ` Krzysztof Kozlowski
2022-10-19 23:31 ` Rob Herring
2022-10-19 15:04 ` [PATCH 1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI " Krzysztof Kozlowski
2022-10-25 14:02 ` Havalige, Thippeswamy
2022-10-19 15:11 ` Krzysztof Kozlowski [this message]
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