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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=GPM41ONK c=1 sm=1 tr=0 ts=6a86e520 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=J8a1EZ1zYi-ZQbc0NmkA:9 a=QEXdDO2ut3YA:10 a=zZCYzV9kfG8A:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-ORIG-GUID: roWCuQr97hbZ-aPMcm_-F-Hwy_UMh0Gu X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODIwMDA4NSBTYWx0ZWRfX+hw6+fywehJk zWLmBz1OITVjNmqGent72M9u0mef/HhBW78XzAG1zHOS+0OXmuu4K7dpxwjhbiYKgqStC5bf3JH LSyQnfsdb59B+w8x/w//eI0QkWDCuvwav9uCRC3XrOZ5SOVcvaMcyAvUoR+h34lwnR3qcJFDAEN jdLkwwfSOgBqJp4F/wmpcSvgrw+NDdTYgRquZqQbd+NLYILtX7bNh+krJvCAvcuifNw+HuBybAa eR34RRy3wxONsUh1dIloR10oBbOe2nbQGmM5mfh0jDkCenGZ67HXsindwvhDf2MirwyW3E8Rnei u8GD9znaomljZlKreOVtf9RtB12kgwkHfoNK93l4a/WZHAJXvUVFPubsYmSfe6Bi/PPfkXIDNb4 vOTNp4Gf+mWh101GG0v3bx8ZWoAYsrcD3lHbTs/zA0Zb4FsLZ+Nu57/Er3tvaaIST1AhB7+wq2R U5baiwuS1prG7OjC5/w== X-Proofpoint-GUID: roWCuQr97hbZ-aPMcm_-F-Hwy_UMh0Gu X-Proofpoint-Spam-Info: AW1haW4tMjYwODIwMDA4NSBTYWx0ZWRfXyyNeLITTMRfq IQZFRQ0IqWPUdWcdIWe1xzAPSWmoAEJz9tOs+pm7yrlLZOqTdM6cCAksWDUpi0NiTG5P0B9TKC2 ptuD3a9S47uzwKoRofcxg7gnJFSr2WY= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-19_06,2026-08-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 spamscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608200085 On 8/20/26 8:36 AM, Qiang Yu wrote: > After a PCIe link goes down, software may still access the BAR (MMIO) > space or configuration space of devices behind that link before recovery > has run. As the link is down, these accesses never complete, resulting in > a storm of Completion Timeout AERs. [...] > static int qcom_pcie_host_init(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > @@ -1775,13 +1832,15 @@ static int qcom_pcie_reset_root_port(struct pci_host_bridge *bridge, > u32 val; > int ret; > > + mutex_lock(&pcie->hw_lock); guard(mutex)(&pcie->hw_lock) This decreases the number of AERs I see while de-authorizing the PCIe link on a TBT3 connection to an ASUS PA27AC monitor from "a whole lot" to just 1 on X1E80100 CRD Tested-by: Konrad Dybcio # X1E80100 CRD + ASUS PA27AC Konrad