From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECF13C00140 for ; Wed, 10 Aug 2022 22:56:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233620AbiHJW4r (ORCPT ); Wed, 10 Aug 2022 18:56:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230227AbiHJW4p (ORCPT ); Wed, 10 Aug 2022 18:56:45 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B166647D9 for ; Wed, 10 Aug 2022 15:56:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660172204; x=1691708204; h=message-id:date:mime-version:to:cc:references:from: subject:in-reply-to:content-transfer-encoding; bh=YKkBtzT3qUfVAd2APMnB/Z38nogl3svTGnsH+cFcuRE=; b=gvJjYUb3GqO66zBue7h2Sg31Tnqf4nO3XIWtKq+vNgcRZVFuWioMk//l t6FEgtA5Ts7MaYoDt02YIbv0j85jmMQVeKMOFu2sDDbghulmSeyvPnma7 bNyScq6n7FnOsaDORS/U8qgHd3D7tVMpE+QKjRYr8B/bBuXKMpamEk0ay d6Ocm7gr8QqYQUCdaKfqOhTuKFx3w2qbfxREVw+mhYBywjnqi0ZvYkJqb DBh+IOWNn8QAs6nAxphQ336LLI0XUctzO+t6YnP3Wu/5Eg0NmCCufuPPJ OUzVRji170PfQLyIjE6LbduS7jw1rsXFOzoipUHmw2CyeeOv/u1XaeIGO w==; X-IronPort-AV: E=McAfee;i="6400,9594,10435"; a="377503840" X-IronPort-AV: E=Sophos;i="5.93,228,1654585200"; d="scan'208";a="377503840" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2022 15:56:43 -0700 X-IronPort-AV: E=Sophos;i="5.93,228,1654585200"; d="scan'208";a="933075526" Received: from sarava2x-mobl1.gar.corp.intel.com (HELO [10.254.67.234]) ([10.254.67.234]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2022 15:56:42 -0700 Message-ID: Date: Wed, 10 Aug 2022 15:56:36 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Content-Language: en-US To: Thomas Gleixner , Dave Hansen , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "Shutemov, Kirill" Cc: "H. Peter Anvin" , linux-kernel@vger.kernel.org, "Gomez Iglesias, Antonio" , Pawan Gupta References: <20220809234000.783284-1-daniel.sneddon@linux.intel.com> <238ea612-5a25-9323-b31f-0a14493db2f7@linux.intel.com> <341ea6e9-d8f3-ee7a-6794-67408abbf047@linux.intel.com> <87r11nu52l.ffs@tglx> From: Daniel Sneddon Subject: Re: [PATCH] x86/apic: Don't disable x2APIC if locked In-Reply-To: <87r11nu52l.ffs@tglx> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/10/22 15:06, Thomas Gleixner wrote: > On Wed, Aug 10 2022 at 12:40, Daniel Sneddon wrote: >> On 8/10/22 11:52, Dave Hansen wrote: >>> On 8/10/22 11:30, Daniel Sneddon wrote: >>>>> If it's going to be on one server CPU that's coming out in ten years, >>>>> then we can hold off. >>>> SPR will certainly be sooner than 10 years, and with distros running on LTS >>>> kernels, it is probably worth backporting. Since this isn't a bug fix (not a sw >>>> bug anyway), is this something I can just CC stable or is there a better way to >>>> say "Yes, this is a new feature, BUT, you really want it anyway"? >>> >>> It it going to be *forced* on those SPR system? In other words, is it a >>> little BIOS switch that users can flip? Is there any non-kernel >>> workaround if a user hits this, or is the entire burden of this going to >>> be foisted on the kernel? >> It won't be forced, BUT, certain features won't be available if the APIC isn't >> locked. According to the documentation SGX and TDX won't be available if you >> don't lock the APIC. So, yes, you don't have to fix it in the kernel, but you >> may lose access to features if you don't. >>> >>> The worst case scenario would be if a user has managed to compile a >>> CONFIG_X86_X2APIC=n kernel and is happily running along until they get a >>> microcode update, reboot and can't boot any more. >> That _shouldn't_ happen as it is only on new hardware, so a ucode update >> _shouldn't_ cause a crash. > > Only on new hardware? The lock mechanism has to be available on _all_ > affected systems which support SGX. See > > https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/resources/intel-sgx-software-and-tcb-recovery-guidance.html I asked the architect and security team that came up with that new MSR if it was going to be backported via ucode updates and I was told no. "Only SPR and newer. See the IA32_XAPIC_DISABLE_STATUS documentation at https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/cpuid-enumeration-and-architectural-msrs.html." So, it appears we have a war between which documentation do we believe! I do have a few follow up questions I'm waiting on being answered to help clarify all this. Thanks, Dan