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Mon, 18 Nov 2024 04:05:07 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Mon, 18 Nov 2024 10:04:37 +0100 From: "Arnd Bergmann" To: "Jacky Chou" , "andrew+netdev@lunn.ch" , "David S . Miller" , "Eric Dumazet" , "Jakub Kicinski" , "Paolo Abeni" , "Rob Herring" , "krzk+dt@kernel.org" , "Conor Dooley" , "Philipp Zabel" , Netdev , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Message-Id: In-Reply-To: References: <20241118060207.141048-1-jacky_chou@aspeedtech.com> <20241118060207.141048-6-jacky_chou@aspeedtech.com> <4b1a9090-4134-4f77-a380-5ead03fd8ba8@app.fastmail.com> Subject: Re: [net-next v2 5/7] net: ftgmac100: add pin strap configuration for AST2700 Content-Type: text/plain Content-Transfer-Encoding: 7bit On Mon, Nov 18, 2024, at 08:51, Jacky Chou wrote: >> Is there a way to probe the presence of 64-bit addressing from hardware >> registers? That would be nicer than triggering it from the compatible string, >> given that any future SoC is likely also 64-bit. I just realized I replied to the wrong email, I meant to send my question as a reply to patch 4/7. The patch for the pin strap looks fine. > There is no register indicated about 64-bit address support in the > ftgmac100 of Aspeed 7th generation. Therefore, we use the compatible > to configure pin strap and DMA mask. Later in the series you just unconditionally write the 64-bit address, so it appears that the ftgmac100 can actually do 64-bti addressing all along, and this doesn't have to be conditional at all, the call to dma_set_mask_and_coherent() only tells the kernel that the device can do it, which should work on all of them. Since the other devices won't have a larger "dma-ranges" configuration in DT, and no RAM above 32-bit addressing, it should have no effect. Just make that part in patch 5 unconditional. Arnd