From: Kartik Rajput <kkartik@nvidia.com>
To: Andi Shyti <andi.shyti@kernel.org>
Cc: ldewangan@nvidia.com, digetx@gmail.com, thierry.reding@gmail.com,
jonathanh@nvidia.com, akhilrajeev@nvidia.com,
smangipudi@nvidia.com, linux-i2c@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v9 2/4] i2c: tegra: Move variant to tegra_i2c_hw_feature
Date: Thu, 22 Jan 2026 23:22:17 +0530 [thread overview]
Message-ID: <e0d498a4-ddfe-40b3-af45-f07d2c5c2e62@nvidia.com> (raw)
In-Reply-To: <aXJe_2JC7KgfBgLa@zenone.zhora.eu>
Hi Andi,
On 22/01/26 23:02, Andi Shyti wrote:
> External email: Use caution opening links or attachments
>
>
> Hi Kartik,
>
>> @@ -280,7 +282,6 @@ struct tegra_i2c_hw_feature {
>> * @base_phys: physical base address of the I2C controller
>> * @cont_id: I2C controller ID, used for packet header
>> * @irq: IRQ number of transfer complete interrupt
>> - * @variant: This represents the I2C controller variant.
>> * @msg_complete: transfer completion notifier
>> * @msg_buf_remaining: size of unsent data in the message buffer
>> * @msg_len: length of message in current transfer
>> @@ -332,13 +333,12 @@ struct tegra_i2c_dev {
>> bool atomic_mode;
>> bool dma_mode;
>> bool msg_read;
>> - enum tegra_i2c_variant variant;
>> };
>>
>> #define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && \
>> - (dev)->variant == TEGRA_I2C_VARIANT_DVC)
>> + (dev)->hw->variant == TEGRA_I2C_VARIANT_DVC)
>> #define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && \
>> - (dev)->variant == TEGRA_I2C_VARIANT_VI)
>> + (dev)->hw->variant == TEGRA_I2C_VARIANT_VI)
>>
>> static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
>> unsigned int reg)
>> @@ -1647,8 +1647,42 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
>> .has_interface_timing_reg = false,
>> .enable_hs_mode_support = false,
>> .has_mutex = false,
>> + .variant = TEGRA_I2C_VARIANT_DEFAULT,
>> };
>
> in v8 I made a question at this point, could you please answer?
>
> Thanks,
> Andi
Are you referring to the following question on v7 of this series, which I've already addressed?
https://lore.kernel.org/linux-tegra/c3cdece5-1bf6-46eb-a668-2ee2a4358a88@nvidia.com/#t
>> why do we need this extra step in this patch and we don't add
>> "variant" directly in tegra_i2c_dev->hw?
>>
> Since we are also introducing match data for DVC and VI variant, I
> decided to split this into two patches.
>
> If you prefer, I can squash following into a single patch:
> * "i2c: tegra: Introduce tegra_i2c_variant to identify DVC and VI"
> * "i2c: tegra: Move variant to tegra_i2c_hw_feature"
Thanks,
Kartik
next prev parent reply other threads:[~2026-01-22 17:52 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-21 15:30 [PATCH v9 0/4] Add I2C support for Tegra410 Kartik Rajput
2026-01-21 15:30 ` [PATCH v9 1/4] i2c: tegra: Introduce tegra_i2c_variant to identify DVC and VI Kartik Rajput
2026-01-21 15:30 ` [PATCH v9 2/4] i2c: tegra: Move variant to tegra_i2c_hw_feature Kartik Rajput
2026-01-22 17:32 ` Andi Shyti
2026-01-22 17:52 ` Kartik Rajput [this message]
2026-01-28 22:17 ` Andi Shyti
2026-01-29 5:30 ` Kartik Rajput
2026-01-21 15:30 ` [PATCH v9 3/4] i2c: tegra: Add logic to support different register offsets Kartik Rajput
2026-01-21 15:30 ` [PATCH v9 4/4] i2c: tegra: Add support for Tegra410 Kartik Rajput
2026-01-21 19:19 ` [PATCH v9 0/4] Add I2C " Jon Hunter
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