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[91.79.162.197]) by smtp.googlemail.com with ESMTPSA id e11sm11378596wrc.9.2019.06.17.07.04.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:04:22 -0700 (PDT) Subject: Re: [PATCH v2 3/6] clocksource/drivers/tegra: Set and use timer's period To: Jon Hunter , Daniel Lezcano , Joseph Lo , Thierry Reding , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org References: <20190610164400.11830-1-digetx@gmail.com> <20190610164400.11830-4-digetx@gmail.com> <3e941c50-ac62-719e-aac1-7072e9a3bcd0@gmail.com> <660f3645-3fa6-175c-75a6-3fcc79e972ad@nvidia.com> From: Dmitry Osipenko Message-ID: Date: Mon, 17 Jun 2019 17:04:21 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.1 MIME-Version: 1.0 In-Reply-To: <660f3645-3fa6-175c-75a6-3fcc79e972ad@nvidia.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 17.06.2019 13:51, Jon Hunter пишет: > > On 14/06/2019 17:45, Dmitry Osipenko wrote: >> 14.06.2019 18:48, Jon Hunter пишет: >>> >>> On 10/06/2019 17:43, Dmitry Osipenko wrote: >>>> The of_clk structure has a period field that is set up initially by >>>> timer_of_clk_init(), that period value need to be adjusted for a case of >>>> TIMER1-9 that are running at a fixed rate that doesn't match the clock's >>>> rate. Note that the period value is currently used only by some of the >>>> clocksource drivers internally and hence this is just a minor cleanup >>>> change that doesn't fix anything. >>>> >>>> Signed-off-by: Dmitry Osipenko >>>> --- >>>> drivers/clocksource/timer-tegra.c | 5 +++-- >>>> 1 file changed, 3 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c >>>> index 810b4e7435cf..646b3530c2d2 100644 >>>> --- a/drivers/clocksource/timer-tegra.c >>>> +++ b/drivers/clocksource/timer-tegra.c >>>> @@ -71,9 +71,9 @@ static int tegra_timer_shutdown(struct clock_event_device *evt) >>>> static int tegra_timer_set_periodic(struct clock_event_device *evt) >>>> { >>>> void __iomem *reg_base = timer_of_base(to_timer_of(evt)); >>>> + unsigned long period = timer_of_period(to_timer_of(evt)); >>>> >>>> - writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | >>>> - ((timer_of_rate(to_timer_of(evt)) / HZ) - 1), >>>> + writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1), >>>> reg_base + TIMER_PTV); >>>> >>>> return 0; >>>> @@ -297,6 +297,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20, >>>> cpu_to->clkevt.rating = rating; >>>> cpu_to->clkevt.cpumask = cpumask_of(cpu); >>>> cpu_to->of_base.base = timer_reg_base + base; >>>> + cpu_to->of_clk.period = DIV_ROUND_UP(rate, HZ); >>> >>> Any reason you made this a round-up? >> >> That's what timer_of_clk_init() does, I assume it should be a more correct variant. > > Sounds to me like this should be 2 patches, because you are changing the > value. This is not just purely cleanup IMO. Indeed, that could be at least mentioned in the commit message. Probably I just assumed that this is such a minor change that not worth anything. A hundred of microseconds is hardly noticeable. I'm not really sure if this really worth a re-spin at this point. Jon, are you insisting? Also, I now see that some drivers use DIV_ROUND_CLOSEST(), maybe it will be even better? Not sure.. given that this is still a microseconds difference.